diff options
| author | Casey Piper <cpiper@codeaurora.org> | 2015-08-03 15:07:10 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:43:02 -0700 |
| commit | 5d2eca04c7583a91c830a3308a7fec81ed906f0a (patch) | |
| tree | aeb413eb4e92016512c167264574b30405b9e578 /drivers/clk | |
| parent | 45ebb6f6ed03acaf98959d09bdc8f1f4ae8ee228 (diff) | |
clk: msm: hdmi: Increase PLL ready bit timeout
When using 4k resolutions at 60fps, the PLL
ready bit will take slightly longer than other
video modes. Increase the timeout value to
ensure that the PLL lock is successful. Also
modify the lane mode values to improve Shmoo
margin with low core voltage.
Change-Id: I9d65535b941e755fe706e4dd61cb357a7a62cdc2
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c index f720b4e07eb5..adb6b86fa142 100644 --- a/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c +++ b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c @@ -318,7 +318,7 @@ #define HDMI_PHY_PHY_REVISION_ID3 (0xC4) #define HDMI_PLL_POLL_MAX_READS 2500 -#define HDMI_PLL_POLL_TIMEOUT_US 100000 +#define HDMI_PLL_POLL_TIMEOUT_US 150000 enum hdmi_pll_freqs { HDMI_PCLK_25200_KHZ, @@ -1418,8 +1418,8 @@ static int hdmi_8996_v3_calculate(u32 pix_clk, cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; cfg->com_vco_tune_ctrl = 0x0; - cfg->tx_l0_lane_mode = (pd.half_rate_mode ? 0x7 : 0x3); - cfg->tx_l2_lane_mode = (pd.half_rate_mode ? 0x7 : 0x3); + cfg->tx_l0_lane_mode = 0x43; + cfg->tx_l2_lane_mode = 0x43; if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { cfg->tx_l0_tx_drv_lvl = 0x25; |