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| * | msm: mdss: add support for DP PLL driver on sdm630Narender Ankam2017-02-27
| | | | | | | | | | | | | | | | | | | | | | | | Add support for DP PLL driver to bring up display port on sdm630. Change-Id: I075581be3c69841a7eb3909b28d5214728717f68 Signed-off-by: Narender Ankam <nankam@codeaurora.org>
* | | clk: qcom: Use the saved current frequency for enable_safe_configTaniya Das2017-03-02
|/ / | | | | | | | | | | | | | | | | A clk_get_rate in the clk_enable path would result in a BUG from sleeping context, as clk_get_rate would hold a mutex when we have already acquired a spinlock in the clk_enable. Change-Id: I7b32292710bbea3565cdc51c79916fddc60f8bba Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | Merge "clk: qcom: osm: program SEQ_REG32 unconditionally"Linux Build Service Account2017-02-25
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| * | clk: qcom: osm: program SEQ_REG32 unconditionallyTirupathi Reddy2017-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Program SEQ_REG32 unconditionally with the L_VAL corresponding to the first virtual corner with MEM ACC level 3. CRs-Fixed: 2011483 Change-Id: I3b8a5bed2c78f0f5f3aae22c4a58c57b75ddf3bb Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
* | | clk: qcom: Enable safe configuration for ahb clock sourceTaniya Das2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid running into issues with the MMNOC RCG being enabled due to an enable request from a secure world entity whilst the HLOS code has disabled its parents, park the RCG at CXO when its disabled. Change-Id: I98e2efaed01ee4e92a457c56f2e276985882dbbb Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | clk: qcom: clk-rcg2: Correct the erroneous RCG configuration during enableDeepak Katragadda2017-02-22
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | If the RCG frequency table does not have CXO as one of its supported frequencies, and if a client calls clk_enable on it prior to setting its rate, the current RCG code would configure it to the lowest supported frequency instead which would then lead the subsequent call to update the configuration to fail because the parent PLLs are not active. Correct this behavior. Also update the index in case cxo_f frequency table is used for rcg configure. Change-Id: Ib2c09f9f503724bafd32b963b5b0ea84da7c4b7b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | Merge "clk: qcom: Remove gcc_hmss_ahb_clk for sdm660"Linux Build Service Account2017-02-21
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| * | clk: qcom: Remove gcc_hmss_ahb_clk for sdm660Amit Nischal2017-02-21
| | | | | | | | | | | | | | | | | | | | | | | | The gcc_hmss_ahb_clk will be controlled by RPM. Remove all control of it from the HLOS clock driver. Change-Id: I26525787352cb0b85937cc005afba7c37a7989ff Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | Merge "clk: qcom: Remove mmssnoc cpu active vote clock for SDM660"Linux Build Service Account2017-02-21
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| * | | clk: qcom: Remove mmssnoc cpu active vote clock for SDM660Taniya Das2017-02-20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | There is no requirement to vote on active only clock of MMSSNOC cpu clock, as the handoff flag for rpm clocks already takes care of the initial vote, until the client puts across a vote. Change-Id: I7804daa804d06ea3a7a81c4cf33156cc7324a542 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | Merge "clk: qcom: Move gcc_usb3_phy_pipe_clk to branch clock"Linux Build Service Account2017-02-21
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| * | | clk: qcom: Move gcc_usb3_phy_pipe_clk to branch clockAmit Nischal2017-02-20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A clk_disable on gate clocks would hold a global spinlock and it would wait for a halt_delay. In some race conditions(due to longer delays for gate clocks) if any other CPU would also invoke a clk_disable then it could result in a spinlock lockup. Avoid this by moving the gcc_usb3_phy_pipe_clk clk to branch clock. CRs-Fixed: 2008439 Change-Id: I177349844c571964637e16a150f93c5912f7dafe Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | Merge "clk: qcom: Remove few multimedia clocks for sdm630"Linux Build Service Account2017-02-21
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| * | | clk: qcom: Remove few multimedia clocks for sdm630Odelu Kukatla2017-02-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the multimedia subsystem clocks are not present in sdm630, so remove them from registering with clock framework. Change-Id: I073dc25fa0a0665a5b9b10c4ea977767a1e286d1 Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* | | | Merge "clk: qcom: Add support to list registers for slew PLL"Linux Build Service Account2017-02-20
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| * | | clk: qcom: Add support to list registers for slew PLLAmit Nischal2017-02-17
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | For slew PLL, register content is required to be displayed for debug purpose. Add support for the same by adding list_register clock ops to clk_alpha_pll_slew_ops. Change-Id: I806edd4d62ff00a4b36d17942afd746b03616534 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | Merge "clk: qcom: Add support to log PLL/RCGR values in case of failure"Linux Build Service Account2017-02-15
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| * | clk: qcom: Add support to log PLL/RCGR values in case of failureTaniya Das2017-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of PLL lock errors or the RCGR fails to update the new configuration, add support to capture all the PLL and RCGR configuration registers as part of kernel logs. Change-Id: Ifb0cefafc30f8796ba17f2d388fb65ed41aae485 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | clk: qcom: Clean up the MSM8996 multimedia clock controller (MMCC) driverOdelu Kukatla2017-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following list of changes have been made 1. Add the missing clocks in multimedia clock controller driver. Also clean up clock flags and parent info for few clocks. 2. Removing clocks which are not controlled by HLOS. 3. MMCC needs to vote for volatge level on rail for the clock frequencies, so add voltage voting in MMCC. 4. Initial rate configuration for MMPLLs. Change-Id: If3d84e52783651b611b624dbc60b18993c0f0b1a Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | Merge "ARM: dts: msm: add mdss node for sdm630"Linux Build Service Account2017-02-11
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| * | | clk: qcom: add MDSS PLL support for sdm630Sandeep Panda2017-02-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the sdm630 compatible string to MDSS PLL driver of_device_id table list, so that initialization of MDSS PLL driver takes place for sdm630 platform. Change-Id: I284ff9c07a4a971260ade399a2f7a605003ccf1d Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | | | Merge "clk: qcom: mdss: update the clk_ops for dp_vco_divided_clk_src_mux"Linux Build Service Account2017-02-11
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| * | | | clk: qcom: mdss: update the clk_ops for dp_vco_divided_clk_src_muxPadmanabhan Komanduru2017-02-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fractional divider values for DP pixel clock RCG needs to be determined dynamically. Add the recalc_rate operation for the DP PLL mux clock dp_vco_divided_clk_src_mux which is the parent of DP pixel clock RCG. This enables the RCG clock to calculate the fractional dividers correctly. Modify the determine rate op for the mux clock to also set the new parent after performing the determine rate operation. Change-Id: Id931a60677380ecee28eb9aec6468548898b812b Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | | | | Merge "clk: qcom: Add qpnp clock divider support"Linux Build Service Account2017-02-10
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| * | | | | clk: qcom: Add qpnp clock divider supportTirupathi Reddy2017-01-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clkdiv module provides a clock output on the PMIC with CXO as the source. This clock can be routed through PMIC GPIOs. Add a device driver to configure this clkdiv module. CRs-Fixed: 1085200 Change-Id: I5e91a954bf5b6adbba8547b04361daf9788cca37 Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
* | | | | | Merge "clk: qcom: update post div bits to be cleared for MMCC/GPU clocks"Linux Build Service Account2017-02-09
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| * | | | | clk: qcom: update post div bits to be cleared for MMCC/GPU clocksTaniya Das2017-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMCC and GPU clocks needs the post div bits to be cleared, so that the clock measure does not account for any previously set div values in the debug mux. Change-Id: I1123e566740518e287692797fa3ab6b316da3bf1 Signed-off-by: Taniya Das <tdas@codeaurora.org>
| * | | | | clk: qcom: Add support for post divider for debug muxTaniya Das2017-02-09
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There could be cases where the post div in different debug muxes could be set previously and not cleared, so add support to clear and set it, in case required. Change-Id: I15fedb4672179cb604804e7cbb0d6afc68bc473b Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | | Merge "clk: qcom: Remove gcc_rx2_qlink_clkref_clk for sdm660"Linux Build Service Account2017-02-09
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| * | | | | clk: qcom: Remove gcc_rx2_qlink_clkref_clk for sdm660Amit Nischal2017-02-07
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gcc_rx2_qlink_clkref_clk is not required by any client, so remove controlling the clock from HLOS clock driver. Change-Id: I20dbb38f3f0fcbcdb3974923f4a0b540153d3fde Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | | | Merge "clk: qcom: keep gcc_bimc_gfx_clk always on for SDM660"Linux Build Service Account2017-02-09
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| * | | | clk: qcom: keep gcc_bimc_gfx_clk always on for SDM660Taniya Das2017-02-07
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep gcc_bimc_gfx_clk always on to prevent a stall during BIMC redirection handshake that occurs as part of a transition between different CCI power modes. Change-Id: Id027d4c3ba3ef15b24cfc2747b1a7b82a206fc31 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | clk: qcom: Update the dp pixel clock flagsTaniya Das2017-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display port pixel clock source is required to propagate the set rate to parent, so update the flags for the same. The lowsvs frequency has got updated to 154MHz, update the same. Change-Id: I67a5ff3b5fb18c2ce986c5f431f4e41a78fe13a5 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | clk: qcom: Update the display port determine rate RCG opsTaniya Das2017-02-07
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | The display port PLL generates only limited set of frequency combinations. As fractional dividers are not required to be used, update the RCG ops to take care of the same. Change-Id: I601273fee044ef128dbc7c2e23bc2d8ce10e31dc Signed-off-by: Taniya Das <tdas@codeaurora.org>
* / / clk: qcom: Add support for cpu clock for sdm630Odelu Kukatla2017-01-31
|/ / | | | | | | | | | | | | | | CPU clock frequencies are different for sdm630, so update the bootup frequency for perf cluster for sdm630. Change-Id: I9da19b0a09ec1c5c7960f9c2fadfe26a3b4c3015 Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* | Merge "clk: qcom: update the clock structures for DP clocks for SDM660"Linux Build Service Account2017-01-28
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| * | clk: qcom: update the clock structures for DP clocks for SDM660Padmanabhan Komanduru2017-01-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the clock names for parents of MDSS display port source clocks for SDM660. The clock frequencies of DP clocks are requested by the MDSS display port driver in order of KHz to avoid integer overflow issues on 32-bit builds. Update the same for DP clock structures in clock driver. Change-Id: Ibfdade6f2db5c9ec7a7ff53ba76e6db53e4e605e Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | | Merge "clk: qcom: Fix uninitialized variable and null pointer exception"Linux Build Service Account2017-01-28
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| * | | clk: qcom: Fix uninitialized variable and null pointer exceptionTaniya Das2017-01-25
| |/ / | | | | | | | | | | | | | | | | | | | | | Initialize the variables before their usage and add null pointer checks before dereferencing pointers. Change-Id: Ibe4140c6e0aa25c37583e6e5e6e2331d86f389aa Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | Merge "clk: qcom: mdss: add support for MDSS DP PLL for SDM660"Linux Build Service Account2017-01-28
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| * | clk: qcom: mdss: add support for MDSS DP PLL for SDM660Padmanabhan Komanduru2017-01-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Model and configure MDSS Display Port PLL for SDM660 target. Add changes to define and register DP VCO, divider and mux clocks as per common clock infrastructure. Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | | clk: qcom: Move the rbcpr clock voltage vote to active onlyTaniya Das2017-01-19
| | | | | | | | | | | | | | | | | | | | | | | | The RBCPR client would not be able to remove it's vote during any low power state, so move the clock to vote on active only voltage. Change-Id: I859ad7eb5b4f604cd8785156a0354ed76d3622c0 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | Merge "clk: qcom: Add support for 19.2Mhz for USB30 utmi clock"Linux Build Service Account2017-01-18
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| * | | clk: qcom: Add support for 19.2Mhz for USB30 utmi clockTaniya Das2017-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB client needs 19.2MHz frequency support for utmi clock, so that it could be requested for. Add support for the same. Change-Id: Icdbf9c5155bdd0ec02d357182d6e020c06a70648 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | Merge "clk: qcom: Move prepare_enable of XO clock before spinlock"Linux Build Service Account2017-01-18
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| * | | | clk: qcom: Move prepare_enable of XO clock before spinlockTaniya Das2017-01-18
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_prepare would hold a mutex and as clk_debug_mux_measure_rate has already acquired a spinlock it would result in a BUG from sleeping context. Avoid this by moving the prepare_enable before acquiring spinlock. Change-Id: Ia405c884663ef80e87ae066df09f1c30134faf2e Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | Merge "clk: qcom: Remove few graphics clock for sdm660"Linux Build Service Account2017-01-18
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| * | | | clk: qcom: Remove few graphics clock for sdm660Taniya Das2017-01-18
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need to left at their default state of ON. Remove controlling them from the linux clock driver to avoid disabling them during late_init. Change-Id: Iefc033998bf87fcc98dfaa1b7321d9cc33dedd5e Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | clk: qcom: Add support for GPLL0 active clock for CPUTaniya Das2017-01-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU clocks would require to vote on active only instance of GPLL0, so add the clock and also update the parent names for the CPU clocks. Change-Id: Id8c7f76170a1cc94fe045b8ba975aaa42c4b3819 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | clk: qcom: Add support for multiple PLL software instancesTaniya Das2017-01-17
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | There could be use cases where the PLL could support various software instances for various peripherals or for cpu. In those cases PLL need to support aggregation logic for the voting and devoting on the PLL. Change-Id: Ie5148a75452dccc555989a454996b945956f94e5 Signed-off-by: Taniya Das <tdas@codeaurora.org>
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