| Commit message (Expand) | Author | Age | ||
|---|---|---|---|---|
| ... | ||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: BCM63xx: Utilize asm/bmips-spaces.h | Florian Fainelli | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: BMIPS: Define BMIPS_FIXADDR_TOP in asm/bmips-spaces.h | Florian Fainelli | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: ingenic: Initial MIPS Creator CI20 support | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: ingenic: Initial JZ4780 support | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: use Ingenic SoC UART driver | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: only detect RAM size if not specified in DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: remove clock.h | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS,clk: migrate JZ4740 to common clock framework | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: replace use of jz4740_clock_bdata | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: Call jz4740_clock_init earlier | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: support newer SoC interrupt controllers | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: Avoid JZ4740-specific naming | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: read intc base address from DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: define IRQ numbers based on number of intc IRQs | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: support >32 interrupts | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: Remove jz_intc_base global | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: drop intc debugfs code | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: register an irq_domain for the interrupt controller | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: probe interrupt controller via DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: use generic plat_irq_dispatch | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: probe CPU interrupt controller via DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip. | Ralf Baechle | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: require & include DT | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: ingenic: Add newer vendor IDs | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: JZ4740: introduce CONFIG_MACH_INGENIC | Paul Burton | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: DEC: Update CPU overrides | Maciej W. Rozycki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: netlogic: remove unnecessary MTD partition probe specification | Brian Norris | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation | Maciej W. Rozycki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init' | Maciej W. Rozycki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: tlb-r3k: Also invalidate wired TLB entries on boot | Maciej W. Rozycki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Take XPA into account | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Take RI/XI bits into account | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Take EHINV bit into account | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Take global bit into account | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Make use of EntryLo bit definitions | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Refactor TLB matching | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: dump_tlb: Use tlbr hazard macros | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: mipsregs.h: Add EntryLo bit definitions | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: hazards: Add hazard macros for tlb read | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: Add SysRq operation to dump TLBs on all CPUs | James Hogan | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: traps: print Exception Code in __show_regs() | Petri Gynther | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: BCM47xx: Read board info for all bcma buses | Rafał Miłecki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: BCM47xx: Extract info about et2 interface | Rafał Miłecki | 2015-06-21 | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | MIPS: BCM47xx: Extract all boardflags to new u32 fields | Rafał Miłecki | 2015-06-21 | |
