summaryrefslogtreecommitdiff
path: root/arch/arm64/include (follow)
Commit message (Collapse)AuthorAge
...
| | * | arm64: vmemmap: use virtual projection of linear regionArd Biesheuvel2016-03-09
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit dfd55ad85e4a7fbaa82df12467515ac3c81e8a3e upstream. Commit dd006da21646 ("arm64: mm: increase VA range of identity map") made some changes to the memory mapping code to allow physical memory to reside at an offset that exceeds the size of the virtual mapping. However, since the size of the vmemmap area is proportional to the size of the VA area, but it is populated relative to the physical space, we may end up with the struct page array being mapped outside of the vmemmap region. For instance, on my Seattle A0 box, I can see the following output in the dmesg log. vmemmap : 0xffffffbdc0000000 - 0xffffffbfc0000000 ( 8 GB maximum) 0xffffffbfc0000000 - 0xffffffbfd0000000 ( 256 MB actual) We can fix this by deciding that the vmemmap region is not a projection of the physical space, but of the virtual space above PAGE_OFFSET, i.e., the linear region. This way, we are guaranteed that the vmemmap region is of sufficient size, and we can even reduce the size by half. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * / asm-generic: Consolidate mark_rodata_ro()Kees Cook2016-03-17
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit e267d97b83d9cecc16c54825f9f3ac7f72dc1e1e upstream. Instead of defining mark_rodata_ro() in each architecture, consolidate it. Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Gross <agross@codeaurora.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Ashok Kumar <ashoks@broadcom.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David Brown <david.brown@linaro.org> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Emese Revfy <re.emese@gmail.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Helge Deller <deller@gmx.de> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Luis R. Rodriguez <mcgrof@suse.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathias Krause <minipli@googlemail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: PaX Team <pageexec@freemail.hu> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ross Zwisler <ross.zwisler@linux.intel.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Toshi Kani <toshi.kani@hp.com> Cc: kernel-hardening@lists.openwall.com Cc: linux-arch <linux-arch@vger.kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-parisc@vger.kernel.org Link: http://lkml.kernel.org/r/1455748879-21872-2-git-send-email-keescook@chromium.org Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: David Brown <david.brown@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | arm64: topology: Export arch_get_cpu_efficiency APITrilok Soni2016-07-08
| | | | | | | | | | | | | | | | | | Export arch_get_cpu_efficiency API since it can be called by the modules. Update topology header file too. CRs-Fixed: 1038542 Change-Id: Ie2ab84b02a8fb4070a0e86f09f52db9aa4163003 Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
* | drivers: GICv3: remove isb() from IAR read functionSatya Durga Srinivasu Prabhala2016-07-05
| | | | | | | | | | | | | | | | | | As per the GICv3 requirement, ISB or other context synchronization operation is needed only during System register writes. CRs-Fixed: 1035275 Change-Id: Ifbe4d974a295b90a511aa10bde5797a1f71972fc Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* | arm64: Add support for app specific settingsSarangdhar Joshi2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support to provide an interface that can be used from userspace to decide whether app specific settings need to be applied / cleared when particular processes are running. CRs-Fixed: 981519 997757 Change-Id: Id81f8b70de64f291a8586150f4d2c7c8f8b4420f Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org> [satyap@codeaurora.org: trivial merge conflict resolution and pull fixes for CR: 997757] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* | jtagv8: add jtagv8 support snapshotShashank Mittal2016-05-24
| | | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit: 89be600 (Merge "msm: camera: Fix KW issues in sensor code") Jtagv8 driver can be used to save and restore debug and ETM registers across power collapse. Change-Id: I1537c92ac86964fdbe9abb012f972d5f3b36047a Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
* | iommu: Add DMA mapper for io-pgtable-fastMitchel Humpherys2016-05-20
| | | | | | | | | | | | | | | | | | | | | | io-pgtable-fast does some underhanded tricks to achieve performance. One of those tricks is that it expects clients to call its map function directly, rather than going through the IOMMU framework. Add a DMA API implementation that goes through io-pgtable-fast. CRs-Fixed: 997751 Change-Id: Iebcafeb630d9023f666078604898069e9f26dfdd Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | drivers: GICv3: Add isb() before mb() per GICv3 requirementSatya Durga Srinivasu Prabhala2016-04-29
| | | | | | | | | | | | | | | | | | | | | | | | commit 0df0dc1c3f0f ("drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registers") added mb() for ICC_IAR1_EL1, ICC_PMR_EL1 and ICC_SGI1R_EL1. But, as per the GICv3 requirement, an "ISB" or other context synchronization operation must precede the "DSB" to ensure visibility of System register writes. Change-Id: I519530cb9c7008aacbad1319f9159887f599dc9b CRs-Fixed: 1004222 Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* | arm64: process management: Add TIF_MM_RELEASEDAbhimanyu Kapur2016-04-07
| | | | | | | | | | | | | | | | | | | | | | | | Add a new task info flag to represent a task whose mm struct has been freed. This is used by the android low memory killer to track tasks whose mm struct has been freed. Change-Id: Id72e67e31fb52e07f01fb6e234b102f63b400aa5 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> [lmark@codeaurora.org: resolve trivial merge conflicts] Signed-off-by: Liam Mark <lmark@codeaurora.org>
* | arm64: cputype: Add Kryo2xx series of the Gold and Silver CPU partsTrilok Soni2016-03-23
| | | | | | | | | | | | | | | | Add part numbers for Kryo2xx seriels of Gold and Silver CPUs. CRs-Fixed: 969563 Change-Id: I11d2e09483075f2496415cb64fb16d2f599f9f7f Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
* | arm64: cputype: Add Qualcomm CPU Implementer ID macroTrilok Soni2016-03-23
| | | | | | | | | | | | | | | | | | Add Qualcomm CPU Implementer ID macro. This is required for the Errata framework. CRs-Fixed: 969563 Change-Id: I354ed0d131c80805915f0a7533351187a89b7e91 Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
* | arm64: fpsimd: add support to enable/disable fpsimd_settings.Sanrio Alvares2016-03-23
| | | | | | | | | | | | | | | | | | | | Add support to enable/disable fpsimd_settings at runtime through kernel command line. fpsimd.fpsimd_settings=0 should disable it. Change-Id: I14bf5f20e36ec4547aad45382cfffc91666a2ff4 Signed-off-by: Sanrio Alvares <salvares@codeaurora.org>
* | arm64: fpsimd: Enable FP(floating-point) settings for msm8996Se Wang (Patrick) Oh2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable FP and SIMD settings for the MSM8996 during the execution of the AArch32 processes and disable these settings when you switch to the AArch64 processes. This commit also adds CONFIG_ENABLE_FP_SIMD_SETTINGS to support FP and SIMD settings. CRs-Fixed: 952837 Change-Id: If9537ca7390d8f08a6b48fb8865d1b349a93bcee Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
* | arm64: cpuinfo: make machine_name as externTrilok Soni2016-03-23
| | | | | | | | | | | | | | | | | | | | of_flat_dt_get_machine_name() API is marked as __init so machine_name should be made as an extern in-order to get it accessed by the cpuinfo.c. In the earlier kernel revisions the usage was restricted to the one file setup.c only and due to which we didn't faced any issue. Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
* | arm64: Add 32-bit sigcontext definition to uapi signcontext.hDavid Ng2016-03-23
| | | | | | | | | | | | | | | | | | The arm64 uapi sigcontext.h can be included by 32-bit userspace modules. Since arm and arm64 sigcontext definition are not compatible, add arm sigcontext definition to arm64 sigcontext.h. Change-Id: I94109b094f6c8376fdaeb2822d7b26d18ddfb2bc Signed-off-by: David Ng <dave@codeaurora.org>
* | arm64: spinlock: Drop the prfm from arch_spin_trylockRohit Vaswani2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per ARM the prefetch for store (prfm pstl1strm) in the arch_spin_trylock routine can lead to some false positives, decreasing the lock performance. On the Cortex-A57 / Cortex-A53, if the memory type is Shareable, then any linefill started by a PST (prefetch for store)/PLDW instruction also causes the data to be invalidated in other cores, so that the line is ready for writing. This will also clear the exclusive marker associated with that cache line (clearing the exclusive monitors). So, in the scenario where we could have multiple cores trying to acquire exclusive access to a cacheline, the removal of prefetch would help with potentially increasing the chances of one of the cores making progress. Example: struct { spinlock_t lock; atomic_t count; } x; We have 2 cores trying to run the below code spin_lock(&x.lock); atomic_inc(&x.count); spin_unlock(&x.lock); lock and count are part of a struct so they fall into the same cacheline. The lock function uses the trylock mechanism as part of debug spinlock. 1. Core1 has acquired the spinlock and is performing the ldxr, add, strx loop in atomic_inc. 2. Core2 are trying to acquire the spinlock. Core1 | Core2 ldxr | | | | prfm pstl1strm add | | | | ldaxr stxr (fails) | | | | Now, the prfm always clears the exclusive marker for the core1 ldxr, so the stxr always fails. This prevents core1 from making progress and releasing the spinlock that core2 is waiting for. This could potentially go on forever and we end up breaking this pattern if the timing changes or if an interrupt triggers. This could happen with more cores trying to acquire the spinlock, cause more prefetches and make the problem worse. By removing the prfm, we allow the stxr @core1 to suceed and atomic_inc completes, allowing core1 to unlock the spinlock and let core2 proceed. Change-Id: I742ab9b6d98aded628e4dcf4a6ec68b8e2a4ec3e Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [abhimany: resolve minor merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | arm64: Add macro for Cortex A72 primary part numberSrinivas Ramana2016-03-22
| | | | | | | | | | | | | | | | | | | | Add a macro containing the MIDR Primary Part Number value needed to identify ARM Cortex A72 processors. Change-Id: I6a0d04930070523c3dba83f3d7869ba75288b531 Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> [abhimany: resolve minor merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | ARM64: Add snapshot of edac.h from msm-3.10Stepan Moskovchenko2016-03-22
| | | | | | | | | | | | | | | | | | | | | | Sync the ARM64 edac header to the version found in msm-3.10 as of commit 142c36711024877a2ec1eb13dbbca38503b26ee3 ("edac: cortex_arm64_edac: Use dbe irq only") to bring in external EDAC API definitions that were missed during the msm-3.18 upgrade. Change-Id: If2dc53858d7a30086a95ea5047bd6b18e44f7e09 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* | ARM64: Enable EDAC support for ARM64 targetsStepan Moskovchenko2016-03-22
| | | | | | | | | | | | | | | | Select EDAC (Error Detection and Reporting) functionality for ARM64 CPUs to allow EDAC drivers for ARM64. Change-Id: I699cbefdba7afab65bf8b60c0d5df06dd3b57773 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* | dma-mapping: fix build when !CONFIG_ARM_DMA_USE_IOMMUShiraz Hashim2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow compilation when CONFIG_ARM_DMA_USE_IOMMU is not selected by providing necessary stub functions and fix few mismatch in function declarations. Following this, remove the changes introduced by f3d8d1061fb0b146b3f5 ("msm: ipa: add empty implementation for iommu functions") as they are no longer needed. Change-Id: I04e3aa63407064e8d9c9550a5cb0a82ede899f00 Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
* | arm64: dma-mapping: remove order parameter from arm_iommu_create_mapping()Mitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm32 recently removed the `order' parameter from arm_iommu_create_mapping: (68efd7d2fb32c: arm: dma-mapping: remove order parameter from arm_iommu_create_mapping()) in order to make the API easier to understand. The arm32 DMA IOMMU mapper has dynamic resizing of the iova bitmap, so there was no reason to keep the `order' parameter around (which was introduced to reduce the size of the bitmap). Although we don't have dynamic iova bitmap reallocation on arm64, we'd still like to get rid of the `order' parameter since it's confusing and doesn't really help much (especially since all known clients on our system are passing order=0). Remove it. Change-Id: I35e32fdfbe05ec434f64a3a316d13c8f43304bc6 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> [pdaly@codeaurora.org Remove gpu/ipa etc modifications] Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* | Revert "arm64: dma-mapping: avoid calling iommu_iova_to_phys"Mitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | This reverts commit 0d02975d9ffd55f1c0fe5db08f45a9ee1d22f354 since it's causing problems for some reason. This should really be debugged but for now just revert it. Change-Id: I31f382c1945cd1cd84dbbd3dfb715009b8442fe9 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | arm64: dma-mapping: avoid calling iommu_iova_to_physMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're currently asking the IOMMU layer to do an iova-to-phys translation in .unmap_page and .sync_single_for_* in the IOMMU DMA mapper. This can be a costly operation since it will need to walk the domain's page tables, either in software or in hardware. Also, in some less-than-ideal implementations of iommu_iova_to_phys this might actually involve sleeping operations. Avoid this overhead by saving the physical address of the buffer in the dma_iommu_mapping structure in .map_page, using it later instead of iommu_iova_to_phys. Change-Id: Ic53b91a222dab01cfcdc34246a847a8c399adfb6 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | arm64: dma-mapping: use ERR_PTR instead of NULL in stubMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | The real arm_iommu_create_mapping function returns an ERR_PTR (not NULL) on failure. Make the stub version match that convention. Change-Id: I1df954ee5b9037778f27fba2e626621740abf782 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | arm64: dma-mapping: make dma_ops constMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | dma_ops should be const since they shouldn't be changing after being defined (there's even a checkpatch warning for this). Convert existing dma_ops to const. Change-Id: Ic27ba9a0832b12cae43cd45c72f053335845fd8f Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> Conflicts: arch/arm64/include/asm/dma-mapping.h arch/arm64/mm/dma-mapping.c
* | arm64: dma-mapping: fix build when !CONFIG_ARM64_DMA_USE_IOMMUMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_ARM64_DMA_USE_IOMMU is not selected, drivers that make use of the ARM DMA IOMMU mapping APIs currently don't link. First instinct might be to add a dependency on CONFIG_ARM64_DMA_USE_IOMMU to those drivers, but they might not actually want to do that because they might have other ways of getting DMA-able memory. Allow compilation when CONFIG_ARM64_DMA_USE_IOMMU is not selected by providing necessary stub functions. Change-Id: I172e00a0748c70676b8ff7555e217a1e6122e3e6 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | arm64: dma-mapping: add support for IOMMU mapperMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems with IOMMUs, it's useful to handle IOMMU mappings in the dma-mapping layer. This is currently supported on arm but not arm64. Add support in arm64 by gratuitously lifting most of the IOMMU-related stuff from dma-mapping.c in arm. The original arm work was done by Marek Szyprowski in [4ce63fcd919c32: "ARM: dma-mapping: add support for IOMMU mapper"]. Change-Id: I1c3c8fe15049fe456751074398fd179ebd2ec64e Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> [pdaly@codeaurora.org Disable upstream implementation] Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* | ARM64: smp: implement arch_trigger_all_cpus_backtrace using IPIRohit Vaswani2016-03-22
| | | | | | | | | | | | | | | | | | | | Since ARM64 doesn't have an NMI, send an IPI to all other CPUs (current cpu prints the stack directly) to capture a backtrace. Change-Id: Ib90494123205b3bbaa0b244ccde6c7e40a560199 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [satyap: trivial merge conflict resolution & compilation fixes] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* | arm64: smp: Add wakeup IPI supportAbhimanyu Kapur2016-03-22
| | | | | | | | | | | | | | | | | | | | Add support for IPI_WAKEUP which is used by hotplug code path to wake up CPU from low power states. Change-Id: I258d05e109a377613064624a5bfda21ab8ea9869 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> [satyap@codeaurora.org: trivial merge conflict resolution] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* | arm64: fix sparse errors from msm-rtbJeremy Gebben2016-03-22
| | | | | | | | | | | | | | | | Correct the the __iomem decorations in __raw_write_logged() and __raw_read_logged(). Change-Id: If4a4f7aff09537772a5f9e386c3c6ada95512457 Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
* | Revert "net, lib: kill arch_fast_hash library bits"Rohit Vaswani2016-03-22
| | | | | | | | This reverts commit 0cb6c969ed9de43687abdfc63714b6fe4385d2fc.
* | msm: pcie: add PCIe bus driver snapshotTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | This PCIe bus driver snapshot is taken as of msm-3.10 commit: 803998b (Merge "ASoC: wcd: don't set autozeroing for conga") This change adds the PCIe bus driver and its dependecies from msm-3.10 to msm-3.14. All the files are as is from msm-3.10. No additional changes were made. Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | drivers: GICv3: Add mb() after the read of the IAR1_EL1 and other registersAbhimanyu Kapur2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the GICv3 architecture spec section "Observability of GIC Register Accsses", architecture execution of the "DSB" gurantees that last interrupt identifier read from ICC_IAR{0,1}_EL1 is observable by the top-level Distributor and by accesses from any processor to the top-level Distributor. Same comment goes for the ICC_PMR_EL1 and ICC_SGI1R_EL1 too. CRs-Fixed: 960754 Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc Signed-off-by: Trilok Soni <tsoni@codeaurora.org> [abhimany: relocate mb()'s to header files] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | arm: traps: emulate a MRCC instruction reading CNTPCT registerSe Wang (Patrick) Oh2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A user space application is planned to support feature for synchronized timestamp among debug packets across peripherals. As part of the feature, it is responsible for providing physical timer count value to user space. If memory mapped timer is used in ARM arch, Usersapce can't read the physical timer count directly with a MRCC ASM instruction. So Kernel traps the instruction and returns the physical timer count. Change-Id: Ia3f0d9c8c06ca9e2204187890c0c57c8640e4f7e Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org> [abhimany: minor merge conflict resolution] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | arm64: dma: Bring back set_dma_ops for other internal uses like dma-removed.cRohit Vaswani2016-03-22
| | | | | | | | Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* | arm64: Add support for KERNEL_TEXT_RDONLYRohit Vaswani2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | When using FORCE_PAGES to allocate the kernel memory into pages, provide an option to mark the the kernel text section as read only. Since the kernel text pages are always mapped in the kernel, anyone can write to the page if they have the address. Enable this option to mark the kernel text pages as read only to trigger a fault if any code attempts to write to a page that is part of the kernel text section. Change-Id: I2a9e105a3340686b4314bb10cc2a6c7bfa19ce8e Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* | arm64: Add support for FREE_PAGES_RDONLYNeeti Desai2016-03-22
| | | | | | | | | | | | | | | | Add config option to trigger page a fault if any code attempts to write to a page on the buddy list Change-Id: Ic5ab791c4117606519c7b9eb4c2876f246d23320 Signed-off-by: Neeti Desai <neetid@codeaurora.org>
* | arm64: Support early fixup for CMALaura Abbott2016-03-22
| | | | | | | | | | | | | | | | | | | | | | Although it isn't architecturally required, CMA regions may need to have attributes changed at runtime. Remap the CMA regions as pages to allow this to happen. Change-Id: I7dd7fa150ce69fdf05f8bf6f76a5ae26dd67ff1b Signed-off-by: Laura Abbott <lauraa@codeaurora.org> [lmark@codeaurora.org: resolve merge conflicts] Signed-off-by: Liam Mark <lmark@codeaurora.org>
* | ARM64: Introduce arch_read_hardware_idAbhimanyu Kapur2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving towards device tree and arm single binary referring to machine descriptor name for hardware id information under /proc/cpuinfo is not suitable for certain soc vendors. Add a hook for soc vendors to supply a per-soc hardware read method. [abhimany: resolved minor merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Conflicts: arch/arm64/kernel/setup.c Change-Id: I6c38a0c0dbf93acec6f6f67498c01c046a13e506
* | CHROMIUM: ARM64: add gpio.h to increase default nrOlof Johansson2016-03-22
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Olof Johansson <olofj@chromium.org> Signed-off-by: David Riley <davidriley@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206724 Git-commit: a98a5186344c027fb53506994ce93f7af8a79960 Git-repo: https://chromium.googlesource.com/chromiumos/third_party/kernel [joonwoop@codeaurora.org: fixed merge conflict in arch/arm64/Kconfig. removed Change-Id tag from commit text.] Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* | lib: iomap: Add MSM RTB supportRohit Vaswani2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioread* and the iowrite* functions and not inlined and hence the RTB logs end up containing the ioread and iowrite functions themselves and not the ones invoking them. Add RTB support to the ioread*and iowrite* functions so that we can get meaningful RTB logs. Note that to avoid multiple RTB logs for ioread* and iowrite* functions, read*_no_log and write*_no_log macros are added. Change-Id: I2315d44c4dfbeee6be4a52f21bf4a20dd9508597 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Signed-off-by: David Keitel <dkeitel@codeaurora.org> Conflicts: arch/arm64/include/asm/io.h
* | msm: redefine __raw_{read, write}v for RTBXiaogang Cui2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | Redefine __raw_readv and __raw_writev for RTB support. Change-Id: Iae7b8e920abc4f23846690d3d1b3d1d933454788 Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org> [abhimany: fix trivial merge conflict] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Conflicts: arch/arm64/include/asm/io.h
* | Revert "arm64: kill flush_cache_all()"Rohit Vaswani2016-03-01
| | | | | | | | | | | | | | | | This reverts the upstream commit 68234df. This is required internally for certain use-cases like flushing cache before reboot to ensure all the data is available in the ramdump. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* | Revert "arm64: Remove unused macros from assembler.h"Rohit Vaswani2016-03-01
| | | | | | | | | | This reverts commit d3127afa712321a2b297cfee358be2cb223f933c. This is required for flush_cache_all to work.
* | arm64: provide dma cache routines with same API as 32 bitLarry Bassel2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APIs __dma_inv_range() and __dma_clean_range() were not exported by the third party patch. Since the functions starting with underscores are not to be directly used by drivers, related functions without the underscores are provided which have the same name and functionality as the 32 bit APIs. Change-Id: Ie0e681614307d9d9a19e58cacfb9b5dff4528977 Signed-off-by: Larry Bassel <lbassel@codeaurora.org> arm64: add defines for dmac_*_range for compatibility with arm32 An earlier patch created defines for dma_*_range APIs to be compatible with arm 32 bit, however it appears these API names have not (at least yet) appeared there, so revise the names to dmac_*_range, which is defined for arm 32 bit so that there is one name defined for both architectures. Change-Id: I6456c02bad73fb54a874dc9925d3d43d9b8be2f2 Signed-off-by: Larry Bassel <lbassel@codeaurora.org> (cherry picked from commit 0930bab0db67cc0d91e52e385e3e061871c6be05)
* | arm64: Mask out 16KB granule in MMFR registerHanumant Singh2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | Memory model feature register specifies the supported page granules. Some ARM cpus may have support for 16KB granules. However currently we donot support 16KB pages sizes. Explicitly mask off that capability if advertised by the cpu. Change-Id: I7daf3f179a5ce103aec7cf103ac198cf64800543 Signed-off-by: Hanumant Singh <hanumant@codeaurora.org>
* | sysctl: add boot_reason and cold_boot sysctl entries for arm64David Collins2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | Define boot_reason and cold_boot variables in the arm64 version of setup.c so that arm64 targets can export the boot_reason and cold_boot sysctl entries. This feature is required by the qpnp-power-on driver. Change-Id: Id2d4ff5b8caa2e6a35d4ac61e338963d602c8b84 Signed-off-by: David Collins <collinsd@codeaurora.org> [osvaldob: resolved trival merge conflicts] Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | arm64: Add pdev_archdata for dmamaskLaura Abbott2016-03-01
|/ | | | | | | | | | | | | | | | | The dma_mask for a device structure is a pointer. This pointer needs to be set up before the dma mask can actually be set. Most frameworks in the kernel take care of setting this up properly but platform devices that don't follow a regular bus structure may not ever have this set. As a result, checks such as dma_capable will always return false on a raw platform device and dma_set_mask will always return -EIO. Fix this by adding a dma_mask in the platform_device archdata and setting it to be the dma_mask. Devices used in other frameworks can change this as needed. Change-Id: I5bfd2aa75798dfdf49d3af70fdd95dfaf2126e8c Signed-off-by: Laura Abbott <lauraa@codeaurora.org> [abhimany: resolve trivial merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2015-12-13
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer fixlets from Thomas Gleixner: "Two trivial fixes which add missing header fileas and forward declarations so the code will compile even when the magic include chains are different" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3: Add missing include for barrier.h irqchip/gic-v3: Add missing struct device_node declaration
| * irqchip/gic-v3: Add missing include for barrier.hMarc Zyngier2015-12-10
| | | | | | | | | | | | | | | | | | | | | | | | Both the 32bit and 64bit versions of the GICv3 header file are using barriers, but neglect to include barrier.h, leading to an interesting splat in some circumstances. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1449483072-17694-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-23 00:49:57 +0000