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* usb: dwc3: Support float charger detectionSriharsha Allenki2019-06-04
| | | | | | | | | | | | | | Chargers on some platforms do not support FLOAT charger detection. On these platforms, the float charger can be detected depending on the state of the DP and DM lines as detected by the PHY. So, on these platforms check for the DP DM line state and if found floating, do not start the peripheral mode and notify PMIC -ETIMEDOUT implying the connected charger is of type float. Change-Id: I6bf54b0d5c143a849ce9ea7bc515d62204ed2f33 Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
* usb: phy-msm-ssusb-qmp: Make vls_clamp_reg as optionalAjay Agarwal2018-07-31
| | | | | | | | | | | Currently the SSUSB QMP PHY driver mandates that vls_clamp_reg be passed from the DTSI. But this register cannot be accessed on a platform on which Linux is a guest OS. This can lead to errors when trying to enable autonomous mode. Work around this situation by making the vls_clamp_reg property as optional. Change-Id: Idb103d9b7bda717a5f12689951a7452c46aa76dd Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
* Revert "usb: host: Add support for usb core indexing"Ajay Agarwal2018-05-16
| | | | | | | | | | This reverts commit 03a86f5cb1adaa2e30a70eefd7bc1ab9509eea46. Remove support for usb core indexing since it is no longer required to send controller number to remote client. Change-Id: I8021c10037a668997782327e4c151d8cac2a2ebb Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
* usb: msm: Add missing android-usb related documentationVivek Kumar2018-04-11
| | | | | | | | This change adds the missing documentation related to device tree bindings for android-usb functionality. Change-Id: Iee24c0a6a333792983a5bea00adaa9a697ab70e3 Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
* usb: host: Add support for usb core indexingHemant Kumar2017-11-24
| | | | | | | | Unique usb core id is used to differentiate between different usb controllers. Change-Id: Ibd886f704e7ecedfbf035b8e5adea2852ddf25bf Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* usb: dwc3-msm: Allow PM suspend in host mode irrespective of runtimePMAjay Agarwal2017-09-27
| | | | | | | | | | | | | | | | | DWC3 driver uses wakeup_source and allows pm_suspend only after entering low power mode as part of runtime suspend. This prevents PM suspend in host mode if connected device's driver doesn't support runtime or selective suspend. Add support in driver where user can specify using dtsi attribute to not use wakeup source in host mode. It will allow system to enter deep sleep or pm_suspend irrespective of runtime PM state of XHCI. On high level below are the changes in default behavior: -Do not use wakeup_source for DWC3 when operating in host mode. -For host mode, devices will suspend upon PM suspend and resumed after PM resume. Change-Id: Ia1d450e6dd99e094e48caf9723a355b7870b54dd Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
* usb: phy: qusb: Allow support for fused tune2 value correctionVijayavardhan Vennapusa2017-08-23
| | | | | | | | | | | | Update the TUNE2 parameter by adjusting the programmed tune2 value with the correction value, if mentioned in dtsi to improve rise/fall times. In case efuse register value is zero after correction, write previous TUNE2 register value as it is instead of writing hardcoded value. And correction value should be between [-10 5] in order to take into consideration while updating TUNE2 register with fused value. Change-Id: Iaf61705bfd0c7b2cb62de8816c912f05876f001c Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
* usb: phy: qusb: Support specifying vdda33 levels from device treeJack Pham2017-05-16
| | | | | | | | | | | | The specific voltage levels for the vdda33 regulator may vary depending on the target. Add an optional device tree property to allow specifying a 3-tuple of voltages for minimum, operating and maximum voltage levels. The minimum level is used when simply powering on, whereas the operating level is used when initializing the PHY. Change-Id: Ia5d301efdb6964434a01264e7aa19421a41e98ca Signed-off-by: Jack Pham <jackp@codeaurora.org>
* Merge "ARM: dts: msm: add sink capabilities to PMI8998 PD PHY"Linux Build Service Account2017-02-07
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| * usb: pd: Read sink capabilities from device treeJack Pham2017-02-06
| | | | | | | | | | | | | | | | | | Add a device tree property to allow specifying the supported set of sink capabilities. If not specified, fall back to a single capability of 5V @ 3A. Change-Id: I394061d9f3070099e35b651ce4b63a7993343bf1 Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | usb: xhci-plat: Add DT parameter to program xhci imod_intervalManu Gautam2017-02-02
| | | | | | | | | | | | | | | | | | | | | | XHCI allows interrupt moderation using imod_interval at 250ns increments. Add DT parameter to specify this imod_value for targets mainly with single CPU to reduce CPU interrupt loads. This allows better balance between CPU usage and performance. CRs-fixed: 1019219 Change-Id: Id479c162da6492caff4dd83de4054fee63b6abc5 Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
* | usb: dwc3: Update core clock rate based on USB port speed.Hemant Kumar2017-01-26
|/ | | | | | | | | | | | | | | Core clock rate can be reduced or increased based on operating speeds. Controller starts in Super Speed mode (higher core clock rate) and it will operate in super or high or full or low speed upon device connection. Update the core clock rate based on bus speed to allows system to operate in better low power state (such as SVS1/SVS2 based on system configuration). High Speed rate for core clock is programmed from dtsi. Super Speed rate will be used if High speed core clock rate is not provided for backward compatibility. Change-Id: I265149d34de19ab50bd7f106a670a7112bfae384 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* USB: dwc3-msm: Add support for voting for PM_QOS_LATENCYVijayavardhan Vennapusa2016-12-21
| | | | | | | | Add required changes to enable to vote for PM_QOS_LATENCY based on number of interrupts fired during certain duration. Change-Id: I92ace85ee7fd40c3f33f1b9f7bdd32469d990d84 Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
* usb: phy: qusb2: Add support to vote for regulator L2aHemant Kumar2016-12-08
| | | | | | | | | | L2a is required to lock the phy PLL upon bus resume when exiting from XO shutdown. This LDO powers REFGEN block which is required to be powered on so that phy PLL gets locked as part of wakeup from XO shutdown. Change-Id: Ia0e3d574de7c78534832e4f8749672eb6fcde1f0 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* USB: dwc3: msm: Add support for vote/devote aggre2_snoc_axi_clkVijayavardhan Vennapusa2016-12-02
| | | | | | | | | | It is required to put/get vote for aggre2_snoc_axi_clk before turning ON USB core clock for read/write transactions to be successful over NOC from USB->DDR. Hence add support for voting aggre2_snoc_axi_clk before enabling USB core clock as part of exiting low power mode. Change-Id: Icb17d65fbbe49d93971905948c3dc9ab17de152a Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
* msm: 8998: Replace cobalt with 8998Runmin Wang2016-11-22
| | | | | | | | | | | Update the code name from msmcobalt to msm8998. As a result, update the filename containing "cobalt" and files content containing "cobalt". CRs-Fixed: 1070840 Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1 Signed-off-by: Runmin Wang <runminw@codeaurora.org> Signed-off-by: Kyle Yan <kyan@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* usb: pd: Support VCONN SwapJack Pham2016-10-14
| | | | | | | | | | | | | | Support incoming VCONN Swap requests by accepting and turning off/on VCONN. Due to HW board limitations, if VCONN is being sourced from the VBUS input we cannot support enabling VCONN while as a sink and greater than 5V has been negotiated on VBUS. In that case, reject the request. Add a device tree property that indicates whether the board is configured for separate VCONN supply. Change-Id: If3a9aa316ae08a80468631f3d536a1b345e21b18 Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: Add support for reset controller frameworkAmit Nischal2016-09-07
| | | | | | | | | | The current api which performs the clock reset is moved to use the reset framework, so support the changes in USB driver for the same. The reset framework requires to get reset handle and perform assert/deassert of the resets. Change-Id: Ifcde1c6af624294cbd1944eaa9b526dd6dcc51de Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* usb: phy: qusb: Update tune1 param from efuse registerVamsi Krishna Samavedam2016-08-30
| | | | | | | | | | Tune1 HSTX_TRIM parameter varies from part to part and needs to be programmed using fused values. Update the code to read the efuse register and update tune1 parameter. On previous platforms this used to be tune2. Change-Id: I7a2efa3c2409ba5dbb1ae9581738518b9457a971 Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
* usb: phy: qusb: Set clamp_dig_n signal based on usb statusVamsi Krishna Samavedam2016-08-30
| | | | | | | | | | | | | Analog and digital power rails connected to the phy can be turned on/off in any order. This may result in random leakage in the phy as it expects certain power rails to be on/off in certain order. Avoid random leakage on qusb2 phy by 1. Disable pll when phy is suspended/disconnected. 2. Reset and assert clamp dig_n signal to put dp/dm lines in high impedance state. Change-Id: I1bafa7f824af8bbb3f67a71b81bf23b0a9c7164e Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
* USB: dwc3-msm: Add support for setting specific frequency for core clockVijayavardhan Vennapusa2016-08-08
| | | | | | | | Add support for setting USB core clock to particular frequency so that core clock frequency can be passed through dts property. Change-Id: If9ff41037d22d7be7f09c9468e8d4cc92280a28e Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
* usb: dwc3: Update VBUS status with USB controllerMayank Rana2016-07-29
| | | | | | | | | | | | | | | It is required to update VBUS status to USB controller using qscratch registers HS_PHY_CTRL and SS_PHY_CTRL interfacing high-speed and super-speed PHYs. This change perfoms same from USB controller's glue driver on starting and stopping peripheral mode based on supported USB speed with USB gadget. It also updates devicetree documentation explicitly mentioning required register sets. CRs-Fixed: 1046503 Change-Id: I92df87c0e2ff54dd7ee513d277cc075eab561019 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qusb: Remove updating VBUS status from QUSB PHY driverMayank Rana2016-07-29
| | | | | | | | | | | | | This change removes updating VBUS status from QUSB PHY driver using QSCRATCH register. New change would be adding same functionality from USB controller driver. - It also updates devicetree documentation and existing supported MSM platforms' USB device node property to accommodate above changes. CRs-Fixed: 1046503 Change-Id: I4573a077bb455ebe3750ab76a91d2593d7e94ea5 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* Merge "usb: phy: Make cfg_ahb_clk optional"Linux Build Service Account2016-07-27
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| * usb: phy: Make cfg_ahb_clk optionalHemant Kumar2016-07-26
| | | | | | | | | | | | | | | | | | | | USB qusb2 and ssusb qmp phy drivers are not required to manage gcc_usb_phy_cfg_ahb2phy_clk clock. It will stay always ON except when in XO-shutdown. RPM will manage this clock. Change-Id: I92647d8ba53bb498b1048ea920a25c04441f6e10 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
| * usb: dwc3: Make cfg_ahb_clk optionalHemant Kumar2016-07-26
| | | | | | | | | | | | | | | | | | dwc3 USB driver is not required to not manage gcc_usb_phy_cfg_ahb2phy_clk clock. It will stay always ON except when in XO-shutdown. RPM will manage this clock. Change-Id: Icc33e63a52b3c5ce83ef2fc56d68eae20278cac0 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* | usb: phy: qusb: Add support for host mode phy init seqDevdutt Patnaik2016-07-19
|/ | | | | | | | Update QUSB2 HS PHY init sequence in host mode to fix enumeration issues due to port reset operation failure. Change-Id: I95daf3e3a833f9daeac6190daa33191f9db8cf26 Signed-off-by: Devdutt Patnaik <dpatnaik@codeaurora.org>
* usb: phy: qusb-v2: Add USB QUSB PHY for newer platformMayank Rana2016-07-07
| | | | | | | | This change adds USB QUSB PHY v2 driver which is compatible for USB QUSB PHY having major revision as 2. Change-Id: I1751352ebbe38d4b8c7886085d15043c2e5244f5 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qmp: Add support to select usb3 phy modeHemant Kumar2016-05-19
| | | | | | | | | | | | qmp phy can run in display port mode or in usb3 mode. It is recommended to explicitly select the usb3 phy mode before programming the phy init sequence, since TCSR_USB3_DP_PHYMODE register is commonly used to select mode between display port driver as well as ssphy driver. Change-Id: I270596868762ccd4f2f2cc9b0daaca647a2bee88 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* usb: pd: Add QPNP Power Delivery PHY driverHemant Kumar2016-05-10
| | | | | | | | | | | | The QPNP PD PHY resides in the PMIC and handles USB Power Delivery data transmission and reception over the CC lines. This driver communicates to this device over SPMI or I2C buses. Introduce APIs that upper layers will use to implement the protocol layer and policy engine. Change-Id: I75dec23c297fd5e07d14741e6627b473012b7a01 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org> Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: dwc3: Add support for GSI event buffer configurationHemant Kumar2016-04-22
| | | | | | | | | Add additional event buffers for GSI based hardware accelerated endpoints and its related configuration. CRs-Fixed: 1003784 Change-Id: Ibedf73690040b8bd872f5621835680a66c22e265 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
* usb: phy: qmp: Add support to use different voltage with core supplyMayank Rana2016-04-13
| | | | | | | | | On newer platform USB QMP PHY needs different voltage supply as core voltage. This change adds required support for the same. CRs-Fixed: 1001463 Change-Id: If100d36bade241dedf28e3cea9e07be192bdfdc2 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qusb: Update QUSB PHY power up functionality for major rev 2Mayank Rana2016-04-07
| | | | | | | | | In new platform, few set of QUSB PHY related operational registers' offset and usage is changed. This change adds QUSB PHY power up and PLL lock functionality for QUSB PHY having major revision 2. Change-Id: Id44c91481d4c184a1991768baf13adad2fae9fb3 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qusb: Use phy_clk_scheme with ref_clk_base_addrMayank Rana2016-04-04
| | | | | | | | | | | Currently phy_clk_scheme related information (i.e. cml or cmos) is used to make decision about how to use ref_clk. On newer platform this functionality is not required. Hence tie phy_clk_scheme with availabiliity of ref_clk_base_addr and perform required ref_clk operation using phy_clk_scheme. Change-Id: If1f264e155a4411df5e037f9f28bc590e9465ac9 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: Add missing msm-dbm related documentationMayank Rana2016-03-23
| | | | | | This change adds documentation related to USB DBM functionality. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qmp: Remove unused devicetree property with QMP PHYMayank Rana2016-03-23
| | | | | | | | This change removes unused devicetree property with QMP PHY as now all QMP PHY related initialization information needs to be provided through devicetree. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qmp: Remove QMP PHY revision based phy_reg_offsetMayank Rana2016-03-23
| | | | | | | | | | This change removes QMP PHY revision based phy_reg_offset from QMP PHY driver. It makes mandatory to have required QMP PHY related register offset through devicetree. It also removes different revision ID related register offset usage and requirement. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qmp: Remove QMP PHY revision based initialization sequenceMayank Rana2016-03-23
| | | | | | | | This change removes QMP PHY revision based initialization sequence from QMP PHY driver. It also makes mandatory to get this sequence from devicetree except if qcom,emulation is set. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: dwc3: msm: add extcon supportJack Pham2016-03-23
| | | | | | | | | | | | | | Add extcon listeners for EXTCON_USB and EXTCON_USB_HOST cable types to be notified of VBUS and ID notifications respectively. Upon notification this will start the controller in either peripheral or host mode. This replaces the handling previously done in the power_supply set_property() callback for PROP_PRESENT and PROP_USB_OTG. The usb_psy will be removed in its entirety following this patch. Change-Id: I22405a0a8da21b4c373895500d8dc4c91d97bc51 Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: phy: qmp: Remove both phy_clk_scheme based init functionalityMayank Rana2016-03-23
| | | | | | | | | Currently QMP PHY driver expects to have both se_clk and diff_clk based PHY initialization sequence from devicetree. This change removes need of both phy_clk_scheme based init sequence as on newer platform QMP PHY only uses one of phy_clk_scheme. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: phy: qusb: Add support to get phy_clk_schemeMayank Rana2016-03-23
| | | | | | | | | This change adds qcom,phy-clk-scheme mandatory property with QUSB PHY driver. qcom,phy-clk-scheme property must have "cml" (i.e. DIFF clock scheme) or "cmos" (i.e. SE clock scheme). Based on this input qusb phy driver uses required reset and initialization sequence. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* USB: PHY: Remove TCSR register based clk_scheme usageMayank Rana2016-03-23
| | | | | | | On newer platform TCSR register based clk_scheme usage is not available. Hence remove its usage from QUSB and QMP PHY drivers. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: Remove DPDM pulsing functionalityMayank Rana2016-03-23
| | | | | | | This change removes DP DM pulsing functionality related support from QUSB PHY driver as it is not required. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* usb: dwc3: Allow controller to enter LPM in bus suspendJack Pham2016-03-22
| | | | | | | | | | | | | | | Add a DT property that decides whether to allow controller low power mode upon bus suspend, which will be invoked by the OTG state machine. It is also required to take the core out of LPM in case ep_queue is called by the upper layers. In this case, remote wakeup sequence will be initiated once the core is out of LPM. [jackp@codeaurora.org: Squashed with dwc3 changes from "usb: dwc3: Add new OTG state OTG_STATE_B_SUSPENDED"] Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: dwc3: core: Disable internal clock gating conditionallyMayank Rana2016-03-22
| | | | | | | | | | | | | Currently USB DWC3 controller's internal clock gating is disabled unconditionally. In few platform, it is possible to enable internal clock gating with controller. Hence this change adds support to disable this functionality conditionally using "snps,disable-clk-gating" device tree property. With this change USB controller's internal clock gating is enabled by default. CRs-Fixed: 851877 Change-Id: I17d43a23d3bff0cb516b952c35c4a13af53f7777 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* USB: dwc3: Add support for fixing superspeed enumeration issueVijayavardhan Vennapusa2016-03-22
| | | | | | | | | | | | | | | | | | Setting SSPHY SUSP bit (bit 17) in GUSB3PIPECTL(0) register might cause device enumerating at high speed mode instead of superspeed mode on some platforms. Hence add workaround by clearing the SSPHY SUSP bit during disconnect and setting it after it is configured to fix this enumeration issue on those platforms. Also add support for disabling U1 and U2 low power modes which could also affect this enumeration issue. CRs-Fixed: 637902 Change-Id: I8668ced09a88b77f37265ab15e89fa9e964bfbe9 Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org> [jackp@codeaurora.org: only add u1/u2 disable bits] Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: dwc3: Set elastic buffer modeJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree property to allow setting the GUSB3PIPECTRL Elastic Buffer Mode (bit 0). By default set the buffer to half-full to work around SuperSpeed link errors. If the property is set, set the buffer to be nominally empty. This change is a combination of two previous commits: USB: dwc3: core: Set elastic buffer mode to zero Currently elastic buffer mode in GUSB3PIPE_CTRL(0) register is set to one. This results in high link error rates and superspeed mode transfer failures if VDDCX is at super turbo mode voltage 1.05V. Hence set elastic buffer mode to zero in GUSB3PIP_CTRL register. usb: dwc3: Do not set half-full elastic buffer On some platforms setting of half-full elastic buffer will cause data corruption and hence we need to avoid this setting. Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org> Signed-off-by: Maya Erez <merez@codeaurora.org> Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: phy: add snapshot of phy-msm driversJack Pham2016-03-22
| | | | | | | | | | This is a snapshot of phy-msm-{hsusb,ssusb,ssusb-qmp,qusb}.c taken as of msm-3.18 commit 9da4ddc18727 (Merge "clk: msm: clock-gcc: Associate gfx rail voting with gfx3d branch") Also replaced ARCH_MSM dependency with ARCH_QCOM in the Kconfig. Signed-off-by: Jack Pham <jackp@codeaurora.org>
* usb: dwc3: msm: Add snapshot of DWC3 MSM driversJack Pham2016-03-22
| | | | | | | | | | | | Add dwc3-msm.c and associated driver files. Note these are based on the downstream implementation and will coexist (for the time being) with dwc3-qcom glue driver until they can eventually be merged. This snapshot is taken as of msm-3.18 commit a3883c356869 (Merge "input: touchscreen: correct condition checks in ITE tech touch driver") Signed-off-by: Jack Pham <jackp@codeaurora.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-11-10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
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