| Commit message (Collapse) | Author | Age |
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On qcom platforms, bootdevice is the primary storage
device. The regulators to this device are left ON by
the bootloaders. Detecting further in the init sequence
that UFS is not the bootdevice entails turning-off of
these regulators without sending PON. This is bad for
the underlying storage device.
Change-Id: I7e9231f0bcf90d8f329146ae2d831bbb5ef8190e
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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UFS device requires a reference clock for
operating in HS (High-speed) gears. This device
reference clock is provided by the dedicated SoC pad
on QCOM platforms. This rail needs to be powered by
1.2v power pads.
Currently, that supply is being controlled
in the ufs phy driver. Phy driver doesn't have any
knowledge of the system-pm state. Hence, it can't
selectively toggle this supply.
Hence, move the control of this supply to ufs driver.
The host driver has the knowledge of system-pm state &
is better equipped to toggle this supply.
Change-Id: Ia19c6e7d9ffb856a01d31ab56ea97a7bb1affae6
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".
Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
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Add support for new UFS PHY that is used in
falcon msm.
This PHY is identical to the final 8996 PHY except it
has been moved to VDDMX and level shifters have been added
between the controller/chip and the PHY.
Change-Id: I50681c877917a58c3d70262597300b0d66b1e3a8
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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Some platforms may have a SOC pin/gpio connected to UFS device's
RST_n to allow the UFS device reset. This change adds support to
trigger device reset on such platforms.
Change-Id: Ie4faa47fb76837dba909f9a3d0dfe11bc69659e1
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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The current api which performs the clock reset is moved to use the reset
framework, so support the changes in ufs driver for the same. The reset
framework requires to get reset handle and perform assert/deassert of the
resets.
Change-Id: I78d833639772cf541e563cbf9fae1aa75ec6a7da
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
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Since msmcobalt RUMI uses QRBTC-V2 UFS PHY, there are a few limitations
that must be applied in order to be able to initialize UFS:
1. UFS should remain in PWM-G1 1-Lane and never change its gear, as other
gears are not stable
2. hibern8 enter/exit should be bypassed
3. we should avoid any power change (as in runtime suspend/resume)
Add "qcom,disable-lpm" property to facilitate disabling of these.
Change-Id: I3f1801da1e2bf1ce8ce98f5ab08211683106ae8c
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
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Add support for QRBTC V2 UFS PHY that is used in msmcobalt rumi platform.
Change-Id: I21ad3f0db23ea16d05ba40593cc7650e1a443702
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
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Add support for new QCOM UFS PHY that is used in
future platforms.
Change-Id: I53f162738668ae9f24f5edb9c42a17f947e68b40
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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Delete renamed orphan files after rebasing 3.18 ufs driver changes
onto 4.4 ufs driver.
Change-Id: Id241ad01bbb0fa74e209c66f8a2d97c05088e33b
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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Current UFS PM QoS design and implementation do not seem to give
the desired increase in performance. This change revisits the
PM QoS implementation trying to improve performance by making
the following changes:
* de-couple voting from clock scaling decision so voting
occurs from the first request and unvoting on the completion
of the last request regardless to clock scaling state.
Otherwise, suspending the PM QoS voting during the time it takes
to decide on clock up-scaling, seems to degrade random access
performance.
* vote on a per-cluster basis by inspecting the request object's
cpu field. This follows the soft-irq allocation scheme in the
block layer, so the cpu to which the block layer schedules the
soft-irq will not be put into deep LPM.
We should note that PM QoS voting using cpu mask for specific
cpus is a feature of the qcom specific PM QoS implementation.
Change-Id: I427d202aeb45cd284a3bb128e26e519212614801
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
[venkatg@codeaurora.org: resolved merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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As of HW major version 2, bit 'UFS_DEV_REF_CLK_EN' which is used to
gate/ungate the ref_clk to external UFS device, was moved into the
UFS register space to UFS_CFG1 register. This change adds support
to appropriately control the device reference clock and it also
adds the missing documentation for the device reference clock control
register address space.
Change-Id: I66a6a75dc5a1cf130b1cee90ae20f9f950edfb3a
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Different platform may have different number of lanes
for the UFS link.
Add parameter to device tree specifying how many lanes
should be configured for the UFS link.
Change-Id: Ida8b13b916f76b3cc7afd3da3d04219e95627678
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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PM QoS request type PM_QOS_REQ_AFFINE_CORES specifies for which CPU
cores the voting is applied to by the cpu affinity mask.
This change defines the cpu mask to be used for the voting in the
device tree node so it can be customized for each target.
Change-Id: I004dea47b42eaf3cdf0489427b2bb894c9982f22
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
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Add PM QOS cpu-dma latency request to the driver.
Latency parameter value is taken from the device tree node
using an optional parameter 'qcom,cpu-dma-latency-us'.
Unless specified, a default of 200us is used.
Change-Id: I3e10da9e65fc7324897c866b0c2a40cc5e6ca070
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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On Qualcomm platforms, there will be many consumers of the source clock
which also supply ref_clk to UFS Device. So even if generic UFS
driver (ufshcd) vote to turn off the source ref_clk, it's very likely that
device ref_clk is still running. Hence some of the qualcomm chipsets have
separate control bit to gate & ungate the UFS ref_clk to device. This
control bit is part of the TLMM register adddress space so it can't be
simulated at clock control bit which means UFS qcom driver has to manually
control this bit to gate or ungate the device ref_clk. This change adds
support for the same.
Change-Id: I3ee1187292eaadfdb552d33c2bb6f58922c9e501
[subhashj@codeaurora.org: resolved merge conflicts, dropped changes to
msm8994.dtsi]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts,
drop changes to include/linux/phy/phy-qcom-ufs.h]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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In-order to enhance storage encryption performance,
an Inline Cryptographic Engine is introduced to UFS.
This patch adds in-line encryption capabilities to the UFS
driver.
Change-Id: Id3cb913498809b32e1f7eba96395b05a9bf3219f
Signed-off-by: Noa Rubens <noag@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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UFS device and link can be put in multiple different low power modes hence
UFS driver supports multiple different low power modes. By default UFS
driver selects the default (optimal) low power mode (which gives moderate
power savings and have relatively less enter and exit latencies) but
we might have to tune this default power mode for different chipset
platforms to meet the low power requirements/goals. Hence this patch
adds option to change default UFS low power mode (level).
Change-Id: I45aaae9f46beb3b5d38bcc6dcbd728e79677276c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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In this change the "compatible" attribute in dts files of ufsphy node
and the "phy-names" attribute in ufs node are changed to a more generic
name.
This is done for apq8084 and for msm8994 targets.
Change-Id: I46176459e9bc877456489e4728b86eecb2c16261
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts & dropped changes to
apq8084.dtsi & msm8994.dtsi]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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This re-factor is required in order to provide a robust way to support
multiple ufs phys. It also creates a better separation between
ufs-msm block, ufs-msm-phy block and the specific phy blocks.
In this change a generic phy handle is created, using the phy driver
framework.
Two ufs phys are currently supported: 28nm and 20nm
This change also includes the required DT changes as in this case,
the driver changes and the DT changes must be placed within the same
change.
Change-Id: I3aa7ed942ed7b54f3a29c9b9dbdeff1861079066
Signed-off-by: Noa Rubens <noag@codeaurora.org>
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[gbroner@codeaurora.org: fix merge conflicts in apq8084 and msm8994
device tree files]
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts, dropped changes to
msm8994.dtsi and fixed compilation errors]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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The UFS host controller on MSM chipsets transfer data over
System NoC to the DDR memory. Add bus bandwidth voting support
based on the speed modes the host communicates with the device
so as to provide optimum throughput while transferring data over
the bus.
Change-Id: I1b407975984985fa108aa9373e2eab08b9027df4
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[gbroner@codeaurora.org: fix merge conflicts - apq8084.dtsi file
location has been previously changed and is already up to date]
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts and also fixed
compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Add MSM UFS host PHY driver which binds with UFSHCD platform
driver exposing vendor specific operations to initialize the
PHY. Since the controller and PHY are tightly coupled in the
system, some of the MSM specific controller register
configuration is also applied inline while initializing PHY.
Add a new compatible property "qcom,ufshc" which specifies the
UFS host controller on MSM platforms. The UFS controller driver
binds with UFS PHY driver using the phandle reference of PHY
devicetree node.
Change-Id: If695a844d03268151c6c846bdfa6cee8ff84491b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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This change turns the UFS variant (SCSI_UFS_QCOM) into a UFS
a platform device.
In order to do so a few additional changes are required:
1. The ufshcd-pltfrm is no longer serves as a platform device.
Now it only serves as a group of platform APIs such as PM APIs
(runtime suspend/resume, system suspend/resume etc), parsers of
clocks, regulators and pm_levels from DT.
2. What used to be the old platform "probe" is now "only"
a pltfrm_init() routine, that does exactly the same, but only
being called by the new probe function of the UFS variant.
Reviewed-by: Rob Herring <robherring2@gmail.com>
Reviewed-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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Add freq-table-hz propery for UFS device to keep track of
<min max> frequencies supported by UFS clocks.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
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Add the support for voting of the regulator powering the
host controller logic.
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
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Add generic clock initialization support for UFSHCD platform
driver. The clock info is read from device tree using standard
clock bindings. A generic max-clock-frequency-hz property is
defined to save information on maximum operating clock frequency
the h/w supports.
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
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UFS devices are powered by at most three external power supplies -
- VCC - The flash memory core power supply, 2.7V to 3.6V or 1.70V to 1.95V
- VCCQ - The controller and I/O power supply, 1.1V to 1.3V
- VCCQ2 - Secondary controller and/or I/O power supply, 1.65V to 1.95V
For some devices VCCQ or VCCQ2 are optional as they can be
generated using internal LDO inside the UFS device.
Add DT bindings for voltage regulators that can be controlled
from host driver.
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Dolev Raviv <draviv@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
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Compatible list is used in commit 03b1781 but is not documented.
Add necessary device tree bindings to describe on-chip UFS host
controllers.
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Santosh Y <santoshsy@gmail.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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