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* iommu/arm-smmu: Add support for regulator deferred disablePrakash Gupta2017-06-05
| | | | | | | | | | | | In case of unmap call, regulator is enabled/disabled. This may introduce additional delay. For clients who do not detach, it's not possible to keep regulator vote while smmu is attached. Add support for regulator deferred disable. The time delay for deferred disable can be set using dt property qcom,deferred-regulator-disable-delay in ms. Change-Id: I462e1999bd81f6332169b24749632d7b247c75c5 Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
* iommu: arm-smmu: Move to using bus bandwidth voting for bus clocksPratik Patel2017-01-20
| | | | | | | | | | | | | | | | | | | | | Bus clocks are managed via bus apis and hence move to using them for enabling bus clocks. The previous method could enable a bus clock at a higher than required frequency, wasting power. The power on sequence is regulator on, bus vote, and then enable remaining clocks. Remove all clocks which are of RPM_SMD type (including mmssnoc_axi_clk) since these are managed by the bus driver. Using an active-only bus vote instead should save power when APPS is power collapsed. Keep the mmss_mnoc_ahb_clk because it is a branch clock type which is not managed by the bus driver. No active-only mode is available for this clock. Change-Id: I3b35d81098b8bd5299b27e85d27aa959e7cf415a Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* iommu/iommu-debug: Add dummy driver for standalone testingMitchel Humpherys2016-05-03
| | | | | | | | | | | | | | | | | | | | | | The IOMMU test framework relies on the `iommus' property, and we currently rely on these methods for making that happen: (1) Clients enabling their DT nodes. (2) We put an `iommus' property in our IOMMU DT nodes themselves. The problem with (1) is that clients aren't always ready during early chip validation. The problem with (2) is that it results in us recursively mapping into the SMMU when we try to do cache maintenance on our page table memory. Fix these problems by introducing a dummy driver with associated device tree bindings that will do absolutely nothing other than wait for the SMMU driver and IOMMU test framework to slurp it up. CRs-Fixed: 1003233 Change-Id: I6a5802aff5bab99d29c6ed9d953a203cbd8015bb Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* Revert "iommu/arm-smmu: add DT option to avoid enabling translations on attach"Patrick Daly2016-03-25
| | | | | | | | | | This reverts commit 5642406b6c3e ("iommu/arm-smmu: add DT option to avoid enabling translations on attach") This device tree option is obsolete. Remove it. Change-Id: I6fc2e3127295b9b597acc21ef5d6b1f78519de68 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* iommu/arm-smmu: add option to enable static context bank allocationSusheel Khiani2016-03-23
| | | | | | | | | | | | | | | | | | | To implement slave side protection, programming of global registers as well as secure context bank registers is handed over to TZ. Now, instead of dynamically allocating context banks, TZ allocates CBs once in pre defined static manner during boot and this allocation is maintained throughout the life of system. Add an option to enable use of this pre-defined context bank allocation. We would be reading through SMR and S2CR registers at run time to identify CB allocated for a particular sid. CRs-Fixed: 959535 Change-Id: I782470a2e4d2a66be17ed2b965ba52b7917592f6 Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
* iommu/arm-smmu: add option to enable halt/resume of SMMUSusheel Khiani2016-03-22
| | | | | | | | | | | | | | | | | | Before SMMU is powered down, SMMU needs to be in idle state prior to power collapse. When 'halt' is received by SMMU, it ensures that no new requests enters and all outstanding requests are completed and generates an acknowledgment for halt request. Add an option to register a notifier on regulator so that SMMU can be halted/resumed when regulator is powered down/up. Some of the targets have built in provision in hardware to halt SMMU when there are no on going transactions. We should keep this option disable for those targets. Change-Id: Ia2f8a934a9d64daefdacd517eb22f09de5eeb273 Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
* iommu/arm-smmu: Add support for dynamic bus scale votingMitchel Humpherys2016-03-22
| | | | | | | | | | | | Some SMMU operations (like register access and ATOS) require downstream buses to be enabled. We've been getting lucky for a long time since other clients have been voting for the buses in question, but recently we've seen some unclocked accesses due to our missing vote. Add support for bus scale voting to the driver. The voting parameters will be provided later in the per-target device tree SMMU configuration. Change-Id: I6b31c887ad817a6628f4234622c73dee046d6442 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add support for DOMAIN_ATTR_DYNAMICJeremy Gebben2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for dynamic domain switching. This feature is only enabled when the qcom,dynamic device tree attribute for an smmu instance. In order to use dynamic domains, a non-dynamic domain must first be created and attached. This non-dynamic domain must remain attached while the device is in use. All domains must be attached before calling any mapping functions, such as iommu_map(). This allows the pagetable setup to be set up during attach based on the hardware configuration for the smmu. Before attaching a dynamic domain, the DOMAIN_ATTR_CONTEXT_BANK must be set to indicate which context bank registers should be used for any register programming. Attaching dynamic domain doesn't cause hardware register programming, but mapping operations may cause TLBI operations. Additionally, the upstream driver or hardware may do other register programming. Because the arm-smmu driver assigns context banks dynamically, the upstream driver should query DOMAIN_ATTR_CONTEXT_BANK on its non-dynamic domain, to ensure the correct value is used for all dynamic domains created. To switch domains dynamically, the upstream driver or hardware must program the TTBR0 and CONTEXTIDR registers with the values from the DOMAIN_ATTR_TTBR0 and DOMAIN_ATTR_CONTEXTIDR attributes for the desired domain. The upstream driver may also need to do other hardware specific register programming to properly synchronize the domain switch. It must ensure that all register state, except for CONTEXTIDR and TTBR0 registers, is restored at the end of the domain switch operation. DOMAIN_ATTR_PROCID may be set to any value for each domain before it is attached. This value is part of the CONTEXTIDR register, but it is not used by the SMMU hardware. Setting a unique value for this attribute in every domain can be useful for debugging. Change-Id: Ib92d06db06832700bdf56265b169ccddfb192698 Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
* iommu/arm-smmu: add option to skip SMR mask sanity checkDhaval Patel2016-03-22
| | | | | | | | | | | | | | | Usually when an SMMU probes we do a sanity check on the SMR registers to make sure they can fully support all of the mask bits. This check can cause problems for use cases where the SMMU is already in use when the SMMU probes. For example, for continuous splash screen support, the stream matching table is programmed before control is even turned over to Linux. Add an option to skip this sanity check. Change-Id: I51a9231fcd8b73034f1a1ca69e4fbb7e632635fa Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org> Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add DT option to avoid enabling translations on attachMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | | There are certain use cases that require the stream matching table to be programmed without actually enabling translations on the SMMU (i.e. leaving SCR0.M=0). For example, when a hypervisor is controlling the stage-2 context bank of a nested configuration where stage-1 needs to be bypassed. This mode of operation is described in the ARM SMMU spec as "stage 1 and stage 2 contexts are valid, but the SMMU is not enabled for stage 1 translation" (Section 2.1: "Overview of SMMU operation"). The easiest way to get the stream-matching table programmed correctly is to program it as usual from Linux but just leave SCR0.M=0. Add a DT option to do this. Change-Id: I065a38f845ae8873bc51221fe64a39b1908032d6 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add TZ workaround for ATOS errataMitchel Humpherys2016-03-22
| | | | | | | | Thulium v1 has an ATOS hardware errata that requires that we call into TZ to do some fixups. Add a DT option to enable this workaround. Change-Id: Ida2fecf1b40ba0f37c9cacc4296b0e8e46db071c Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* soc: qcom: add library for SMMU TZ interfaceMitchel Humpherys2016-03-22
| | | | | | | | | | | Some targets require calling into TZ for various bits of SMMU configuration. Add a library to provide a clean interface for such configuration. Change-Id: I1dc5cd21d4a09e321039d69cc760eaf6f356c6cf Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> [pdaly@codeaurora.org Resolve minor conflicts] Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* iommu/arm-smmu: add DT option to make address size faults fatalMitchel Humpherys2016-03-22
| | | | | | | | | | Some hardware requires special fixups to recover from address size faults. Rather than applying the fixups add an option to just BUG since address size faults are due to a fundamental programming error from which we don't care about recovering anyways. Change-Id: Ibb70e4ec00683562dae9f3239b286daa5deabd45 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: implement workaround for context fault hang errataMitchel Humpherys2016-03-22
| | | | | | | | | | There is a hardware errata that could result in bus hang during context fault processing. The work around given by the hardware team is to issue a TLBSYNC and terminate the transaction. Implement the workaround and provide a DT option to activate it. Change-Id: Iede30ff68676188af1249fd2fd776bc84f224dc6 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add DT option to skip certain initializationMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | On some targets, context banks can be dedicated for use by other execution environments outside of Linux. However, we currently assume that we own all of the context banks during SMMU initialization in arm_smmu_device_reset. This can mess up the other execution environments since we are trampling on their SCTLR, SMR, and S2CR. Provide a DT option to skip this initialization altogether, since the other execution environment should have already initialized the SMMU anyways. Change-Id: I0ed4cbbcdad596f9201f83cb7d0e28a289e18a6e Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add support for saving config registersMitchel Humpherys2016-03-22
| | | | | | | | | | Some hardware is capable of retaining register values during power collapse. Add an option (configurable via DT) to enable this feature. This is implemented by always enabling/disabling regulators every time clocks are enabled/disabled. Change-Id: I89d9a4f4a2eb29f0868b309d55a77cc4ed50e22e Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: workaround some ATOS hw errataMitchel Humpherys2016-03-22
| | | | | | | | | Thulium has a hardware errata that requires that the SMMU be halted and that a TLBIALL be issued before the ATOS command. Add a DT option that implements this workaround. Change-Id: Ic40c7b93d64eebb97fe77082d8335debab624af1 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: program implementation defined registers on attachMitchel Humpherys2016-03-22
| | | | | | | | | Some platforms require certain implementation-defined registers to be programmed when first attaching to the SMMU. Add support for this via specifying register offset, value pairs in the device tree. Change-Id: Iac2fe42684c3849a24d0d1251a206954262257c5 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: program ACTLR register for qcom SMMUsMitchel Humpherys2016-03-22
| | | | | | | | | | The ACTLR must be programmed according to the hardware design in order for the coherent table walk feature to work on certain Qualcomm hardware. Provide a new compatible string ("qcom,smmu-v2") to indicate the relevant hardware and do the programming as needed. Change-Id: I7e807384c821fc3d07274f35726abb28d0d75ee0 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: support buggy implementations with invalidate-on-mapMitchel Humpherys2016-03-22
| | | | | | | | | Add a workaround for some buggy hardware that requires a TLB invalidate operation to occur at map time. Activate the feature with the qcom,smmu-invalidate-on-map boolean DT property. Change-Id: I081a279fead983ae3d736b44cda371078e55a750 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add support for specifying regulatorsMitchel Humpherys2016-03-22
| | | | | | | | | On some power-constrained platforms it's useful to disable power when a device is not in use. Add support for specifying regulators for SMMUs and only leave power on as long as the SMMU is in use (attached). Change-Id: I87191d325423f160ddd4b71f5bf3a92f4942b821 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* iommu/arm-smmu: add support for specifying clocksMitchel Humpherys2016-03-22
| | | | | | | | | | | | | | | | | On some platforms with tight power constraints it is polite to only leave your clocks on for as long as you absolutely need them. Currently we assume that all clocks necessary for SMMU register access are always on. Add some optional device tree properties to specify any clocks that are necessary for SMMU register access and turn them on and off as needed. If no clocks are specified in the device tree things continue to work the way they always have: we assume all necessary clocks are always turned on. Change-Id: Ie42647e117b51a45c939aa479487fa4b5f101c68 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-11-10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
| * dt-bindings: Consolidate Exynos SoC bindingsKrzysztof Kozlowski2015-10-24
| | | | | | | | | | | | | | | | | | | | | | Exynos SoC Device Tree bindings are spread over arm/exynos/ and arm/samsung/ directories. There is no need for that separation and it actually confuses. Put power domain bindings under power/ and remaining samsung-boards.txt under arm/samsung/. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| |
| \
*-. \ Merge branches 'x86/vt-d', 'arm/omap', 'arm/smmu', 's390', 'core' and ↵Joerg Roedel2015-11-02
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | 'x86/amd' into next Conflicts: drivers/iommu/amd_iommu_types.h
| | * iommu/arm-smmu: Add support for MSI on SMMUv3Marc Zyngier2015-10-15
| |/ |/| | | | | | | | | | | | | | | | | Despite being a platform device, the SMMUv3 is capable of signaling interrupts using MSIs. Hook it into the platform MSI framework and enjoy faults being reported in a new and exciting way. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [will: tidied up the binding example and reworked most of the code] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * Documentation: dt: Update OMAP iommu bindings for DRA7 DSPsSuman Anna2015-10-14
|/ | | | | | | | | | | | | | | | | | | The DSP processor sub-systems on DRA7xx have two MMU instances each, one for the processor core and the other for an internal EDMA block. These MMUs need an additional shared register to be programmed in the DSP_SYSTEM sub-module to be enabled properly. The OMAP IOMMU bindings is updated to account for this additional syscon property required for these DSP IOMMU instances on DRA7xx SoCs. A new compatible "ti,dra7-dsp-iommu" is also defined to distinguish these devices specifically from other DRA7 IOMMU devices. An example of the DRA7 DSP IOMMU nodes is also added to the document for clarity. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
*---. Merge branches 'arm/omap', 'arm/msm', 'arm/smmu', 'arm/tegra', 'x86/vt-d', ↵Joerg Roedel2015-08-25
|\ \ \ | | | | | | | | | | | | 'x86/amd', 'ppc/pamu' and 'core' into next
| | * | iommu/arm-smmu: Sort out coherencyRobin Murphy2015-07-31
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we detect whether the SMMU has coherent page table walk capability from the IDR0.CTTW field, and base our cache maintenance decisions on that. In preparation for fixing the bogus DMA API usage, however, we need to ensure that the DMA API agrees about this, which necessitates deferring to the dma-coherent property in the device tree for the final say. As an added bonus, since systems exist where an external CTTW signal has been tied off incorrectly at integration, allowing DT to override it offers a neat workaround for coherency issues with such SMMUs. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | Documentation: dt: Add #iommu-cells info to OMAP iommu bindingsSuman Anna2015-08-03
|/ / | | | | | | | | | | | | | | | | The OMAP IOMMU bindings is updated to reflect the required #iommu-cells property. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* | iommu/arm-smmu: Skip the execution of CMD_PREFETCH_CONFIGZhen Lei2015-07-08
| | | | | | | | | | | | | | | | | | | | | | Hisilicon SMMUv3 devices treat CMD_PREFETCH_CONFIG as a illegal command, execute it will trigger GERROR interrupt. Although the gerror code manage to turn the prefetch into a SYNC, and the system can continue to run normally, but it's ugly to print error information. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> [will: extended binding documentation] Signed-off-by: Will Deacon <will.deacon@arm.com>
* | Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMUWill Deacon2015-05-29
|/ | | | | | | | This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* Merge tag 'dt-for-linus' of ↵Linus Torvalds2015-02-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
| * ARM: dts: convert to generic power domain bindings for exynos DTMarek Szyprowski2015-01-24
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch replaces all custom samsung,power-domain dt properties with generic power domain bindings and updates documentation Samsung's devices referring to old binding. Suggested-by: Kevin Hilman <khilman@kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> [javier.martinez@collabora.co.uk: tested on the Exynos5800 Peach Pi Chromebook] Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* | iommu/ipmmu-vmsa: Add device tree bindings documentationLaurent Pinchart2015-01-16
|/ | | | | Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
* dt-bindings: iommu: Add documentation for rockchip iommuDaniel Kurtz2014-11-03
| | | | | | | | | Add binding documentation for Rockchip IOMMU. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Simon Xue <xxm@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: support MMU-401Robin Murphy2014-09-16
| | | | | | | MMU-401 is similar to MMU-400, but updated with limited ARMv8 support. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
*-. Merge branches 'x86/vt-d', 'x86/amd', 'arm/omap', 'ppc/pamu', 'arm/smmu', ↵Joerg Roedel2014-07-31
|\ \ | | | | | | | | | 'arm/exynos' and 'core' into next
| | * devicetree: Add generic IOMMU device tree bindingsThierry Reding2014-07-31
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a generic device tree binding for IOMMU devices. Only a very minimal subset is described here, but it is enough to cover the requirements of both the Exynos System MMU and Tegra SMMU as discussed here: https://lkml.org/lkml/2014/4/27/346 Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Olof Johansson <olof@lixom.net> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| * iommu/arm-smmu: remove support for chained SMMUsWill Deacon2014-07-03
|/ | | | | | | | | | | | | | | | The ARM SMMU driver has supported chained SMMUs (i.e. SMMUs connected back-to-back in series) via the smmu-parent property in device tree. This was in anticipation of somebody building such a configuration, however that seems not to be the case. This patch removes the unused chained SMMU hack from the driver. We can consider adding it back later if somebody decided they need it, but for the time being it's just pointless mess that we're carrying in mainline. Removal of the feature also makes migration to the generic IOMMU bindings easier. Signed-off-by: Will Deacon <will.deacon@arm.com>
* documentation/iommu: Add note on existing DT binding statusShaik Ameer Basha2014-05-14
| | | | | | | | | | The current dt binding for Exynos System MMU can be changed, if found incompatible with the support for "Generic IOMMU Binding". This patch adds a note to the binding documentation stating the same. Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* documentation: iommu: Add binding document of Exynos System MMUCho KyongHo2014-05-13
| | | | | | | | | This patch adds a description of the device tree binding for the Samsung Exynos System MMU. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
*-. Merge branches 'iommu/fixes', 'arm/smmu', 'x86/amd', 'arm/omap', ↵Joerg Roedel2014-04-02
|\ \ | | | | | | | | | 'arm/shmobile' and 'x86/vt-d' into next
| | * Documentation: dt: add OMAP iommu bindingsFlorian Vaussard2014-03-04
| |/ |/| | | | | | | | | | | | | | | | | | | | | This patch adds the iommu bindings for all OMAP2+ SoCs. Apart from the standard bindings used by OMAP peripherals, this patch uses a 'dma-window' (already used by Tegra SMMU) and adds two OMAP custom bindings - 'ti,#tlb-entries' and 'ti,iommu-bus-err-back'. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> [s-anna@ti.com: split bindings document, add dra7 and bus error back] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
| * documentation/iommu: update description of ARM System MMU bindingAndreas Herrmann2014-02-24
|/ | | | | | | | | | | | | This patch adds descriptions for new properties of the device tree binding for the ARM SMMU architecture. These properties control arm-smmu driver options. Cc: Grant Likely <grant.likely@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com> [will: removed device isolation property, as this has been dropped and fixed up spacing in documentation] Signed-off-by: Will Deacon <will.deacon@arm.com>
* documentation/iommu: Add description of ARM System MMU bindingWill Deacon2013-06-25
| | | | | | | | | | | | | This patch adds a description of the device tree binding for the ARM System MMU architecture. Cc: Rob Herring <robherring2@gmail.com> Cc: Andreas Herrmann <andreas.herrmann@calxeda.com> Cc: Joerg Roedel <joro@8bytes.org> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Andreas Herrmann <andreas.herrmann@calxeda.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
* iommu/tegra: smmu: Add device tree support for SMMUHiroshi Doyu2012-06-25
| | | | | | | | | | | | | The necessary info is expected to pass from DT. For more precise resource reservation, there shouldn't be any overlapping of register range between SMMU and MC. SMMU register offset needs to be calculated correctly, based on its register bank. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu/tegra: gart: Fix register offset correctlyHiroshi DOYU2012-05-11
| | | | | | | | | | DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* iommu: tegra/gart: Add device tree supportThierry Reding2012-04-16
This commit adds device tree support for the GART hardware available on NVIDIA Tegra 20 SoCs. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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