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* Revert "msm: kgsl: Disallow L2PC during wake up from SLUMBER"Kyle Piefer2019-12-23
| | | | | | | | | This reverts commit 5344e5c78f5820dfa34cfcea4572d8e347a018ce. The change negatively impacted performance. CRs-Fixed: 2120475 Change-Id: Ib6ff329a3501e77d990c2e9502ed35e041f730c8 Signed-off-by: Kyle Piefer <kpiefer@codeaurora.org>
* msm: kgsl: Add disable-wake-on-touch devicetree propertyHareesh Gundu2017-08-08
| | | | | | | | | | Add a devicetree "disable-wake-on-touch" property support to disable GPU wake up on touch input events. This will help save power in case of unintended taps and swipes, for example, when the screen is wet. Change-Id: I35768dc78c473272472aaf9c0e09e66d75817b2c Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Disallow L2PC during wake up from SLUMBERGaurav Sonwani2017-07-31
| | | | | | | | | | Add a PM QOS request to disallow L2PC during wake up from SLUMBER state. This is required to improve queue to submit time for first set of GPU commands which results in GPU wake up. Change-Id: Iad1a6dfdf9e1fe034eef4fae526138d724bdd3eb Signed-off-by: Gaurav Sonwani <gsonwani@codeaurora.org>
* Merge "msm: kgsl: Map GPU QTimer through GPU IOMMU"Linux Build Service Account2017-03-10
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| * msm: kgsl: Map GPU QTimer through GPU IOMMUJonathan Wicks2017-02-28
| | | | | | | | | | | | | | | | Map the GPU QTimer area as a global into the GPU IOMMU so that the GPU can access the QTimer. Change-Id: If50bd36681123adde7e3a37644c41316f101154c Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* | msm: kgsl: Add GPU Cx ipeak client support on SDM660Rajesh Kemisetti2017-02-27
|/ | | | | | | | | | | | | To handle Cx peak current limit on SDM660, GPU needs to call Cx ipeak driver APIs when it switches between threshold points. Cx ipeak driver will throttle cDSP frequency if all the clients are running at their respective threshold frequencies to limit Cx peak current. Change-Id: I5ffcf1a42523072d2b8b7bc0022eb3cc067acbb9 Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* msm: kgsl: Do a midframe sampling of power stats if enabledPrakash Kamliya2016-12-22
| | | | | | | | | | | | Currently we sample power stats at the expiry of cmdbatch. In cases where cmdbatch takes a long time to finish the job, it delays power stats sampling, in effect it delays DCVS decision for changing the frequency. Do a midframe power stats sampling and feed it to DCVS if it is enabled. Change-Id: I547d792b38649aa1d60525b0dc335791b37989fd Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* msm: kgsl: Add trace ID support for graphics coresightLokesh Batra2016-12-07
| | | | | | | | | Add the support for trace ID for coresight. This ID is will be defined in the respective device tree file. Change-Id: I78ba05ed05b54fdc0f4d4f55c468f90f39c821f1 Signed-off-by: Lokesh Batra <lbatra@codeaurora.org> Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* Merge "msm: kgsl: Add qcom,gpu-quirk-disable-lmloadkill"Linux Build Service Account2016-11-10
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| * msm: kgsl: Add qcom,gpu-quirk-disable-lmloadkillHarshdeep Dhatt2016-11-08
| | | | | | | | | | | | | | | | | | | | | | Add a quirk to set LMLOADKILLDIS bit in A5XX_VPC_DBG_ECO_CNTL and clear LMLOADKILLDIS bit in A5XX_HLSQ_DBG_ECO_CNTL registers. This is done to avoid a VPC corner case with local memory(LM) which leads to corrupt internal state on A540 and its derivatives. CRs-Fixed: 1036444 Change-Id: I31008433f19924bb35560d3e35fe0665e73751d5 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | msm: kgsl: Allow mempools to configure from the device treeHareesh Gundu2016-11-07
|/ | | | | | | | | | Add driver support to configure mempools from the device tree. This will enable mempools to configure per device specific and reduces the high kgsl memory usage based on configuration. CRs-Fixed: 1064046 Change-Id: I0a7e36b7e1fef9d42a4c0fe33d69a4debf15af2f Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* Merge "msm: kgsl: Remove obsolete IOMMU domain attribute"Linux Build Service Account2016-10-11
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| * msm: kgsl: Remove obsolete IOMMU domain attributeMitchel Humpherys2016-09-26
| | | | | | | | | | | | | | | | | | The DOMAIN_ATTR_COHERENT_HTW_DISABLE IOMMU domain attribute is being removed. SMMU coherency will be configured through the SMMU device tree nodes moving forward. Remove the obsolete option. Change-Id: I4bbbfb90fe172e048cc9504c4e6be5f36501b485 Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | msm: kgsl: Add and link gpu sysfs nodesHarshdeep Dhatt2016-10-05
|/ | | | | | | | | | | | Add new sysfs nodes which satisfy a generic format requested by customer. Also add a new node to track GPU temperature. Create links to these nodes at a generic location: /sys/kernel/gpu/ CRs-Fixed: 1064728 Change-Id: I414a07ff4f9ee14b8f882d15644b06a73d5fcf76 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* msm: kgsl: remove un-used GPU power statesGeorge Shen2016-08-25
| | | | | | | | | | DEEP-NAP and SLEEP states are not used in targets of previous two generations. They are neither saving GPU power, nor saving system power. Remove to reduce maintenance overhead. CRs-Fixed: 1053516 Change-Id: If2fc2701548f90bb7ea9559a87752e13a7b0f736 Signed-off-by: George Shen <sqiao@codeaurora.org>
* msm: kgsl: remove GFX retention supportGeorge Shen2016-08-22
| | | | | | | | | | | GFX retention mode does not save GFX rail power. The feature increased MX rail power. Fixing the problem requires more overhead than removing it. The feature has never been enabled in any targets. So remove the feature. CRs-Fixed: 1053516 Change-Id: I5f118138eca307f7cc16405ff9c8897ecd510c12 Signed-off-by: George Shen <sqiao@codeaurora.org>
* msm: kgsl: Disable RB sampler data path optimizationSunil Khatri2016-08-10
| | | | | | | | | | | Disable RB sampler data path DP2 clock gating optimization for 1-SP A5XX GPU's. Optimization leads to precision difference during interpolation which cause rendering difference between Binning and Direct rendering mode. CRs-Fixed: 1040638 Change-Id: I40d1ce2f5db0ed75453feda5c31152f8201b8697 Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
* msm: kgsl: Map GPU QDSS STM through GPU IOMMUJonathan Wicks2016-07-19
| | | | | | | | | | | Map the GPU QDSS STM area as a global into the GPU IOMMU so that GPU traces can be routed to QDSS. Enable the gpuaddr and size of the area to be queried from userspace. CRs-Fixed: 1031648 Change-Id: I2e32522a42508a6bee088c95dc56a13935dd691c Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* Merge "msm: kgsl: Disable GPU software clockgating on A540"Linux Build Service Account2016-07-15
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| * msm: kgsl: Disable GPU software clockgating on A540Oleg Perelet2016-07-13
| | | | | | | | | | | | | | | | | | GPMU & CRC perform more effective idle clock control than software clock gating. CRs-Fixed: 973565 Change-Id: Ifd45878a65b7da4167d2caa30b3acffd427ad72e Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Disable GPU isense clock below nominal power levelOleg Perelet2016-07-13
|/ | | | | | | | | By disabling isense clock below nominal level we'll remove vote for CX rail and save power. CRs-Fixed: 973565 Change-Id: If4a13b3eca117fc2ff9c32ca3a24eb8b8e70b4fe Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: Add gcc_gpu_iref_clk to list of GPU clocksOleg Perelet2016-06-29
| | | | | | | | GPU will vote off gcc_gpu_iref_clk when going to low power modes. CRs-Fixed: 1024948 Change-Id: I13b7a70f1fa748f2f4cdfb485dda2f7857e0b3d2 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* ARM: dts: msm: Increase snapshot size for msm8996 and msmcobaltHarshdeep Dhatt2016-06-07
| | | | | | | | | | | | Increase the size of snapshot static region to 1MB in the device tree file for a5x targets which have preemption enabled. This increase is needed to accommodate preemption records and preemption history records. This overrides the snapshot size specified in the driver code. CRs-Fixed: 999360 Change-Id: I2cd27481cc0fb189e35ea44709fe27ad0884fcfd Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* msm: kgsl: Add pm_qos_cpu_mask_latency to avoid L2PC on mask CPUDivya Ponnusamy2016-03-25
| | | | | | | | | Add a l2pc-cpu-mask-latency in device tree. This latency is used in kgsl_pwrctrl_update_l2pc() API to avoid L2PC on masked CPUs by giving reduced latency value. Change-Id: I0447977bce5ed5c09a863b03bb42b9428686a9f5 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* msm: kgsl: Add quirk for masking out hang detect signalsShrenuj Bansal2016-03-23
| | | | | | | | | | Add a quirk to mask out the RB 1-3 activity signals in the hang detection logic. Set this quirk in the devicetree for 8996v2 and v3. CRs-Fixed: 978849 Change-Id: I63073b5973644453e775b41a9361de55d7933a07 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* msm: kgsl: Submit a set of critical packets right after ME initShrenuj Bansal2016-03-23
| | | | | | | | | | During the initialization sequence, submit a set of important packets to the GPU in order to pre-load the I-cache with the critical ucode instructions. CRs-Fixed: 978777 Change-Id: Ic6a17b24d8c3aa383af8e25cf9ef771459d65796 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* msm: kgsl: Specify the initial pwrlevel for each speed binSuman Tatiraju2016-03-23
| | | | | | | | | | Some platforms support multiple GPU clock plans based on the speed bin in the efuse. Specify the wake up frequency of each speed bin individually to wake the gpu at the correct powerlevel. CRs-Fixed: 967494 Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Set the DDR high bank bit if specified in the device treeJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | | | | On 5XX targets we need to program the bit of the highest DDR bank into a number of registers, one of which is protected which would cause problems if the user mode driver tried to write to it. Specify the high bank bit in the device tree files, set the problematic register in the kernel and then pass the value up to the user mode driver as a property and let them program the other registers. This makes the device tree the authoratative source of the high bit value which is exactly how it should be. If the value isn't specified by the device tree for whatever reason return an error for the property request - that will give the UMD a clue that the value wasn't specified and they should just set a default. CRs-Fixed: 970272 Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add disable-busy-time-burst to disable ceiling thresholdDivya Ponnusamy2016-03-23
| | | | | | | | | | Add a devicetree property disable-busy-time-burst to disable ceiling threshold in the governor. The ceiling threshold cause busy time burst that switch power level for large frames based on busy time. Change-Id: I44f8a51e0aa49bb0b2210703f57874fd5f219c18 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* msm: kgsl: Read speed bin information from device treeSuman Tatiraju2016-03-23
| | | | | | | | | | | | Speed bin information is sometimes written to efuses to specify a GPU frequency plan available on a platform. The current code only supports reading the efuses for msm8996v3. Hence specify it in the platform device tree node to support multiple platforms. CRs-Fixed: 967494 Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Enable GPU-BIMC clocks from kernel driverSunil Khatri2016-03-23
| | | | | | | | | | | | | | | Enable direct programming of GPU-BIMC interface clocks from kernel driver when moving in and out of TURBO. This is done only for targets with a device tree entry defined for GPU-BIMC interface. This is done because some targets do not support B/W requirement of GPU at TURBO, for such targets we need to program the GPU-BIMC interface clocks with TURBO values to meet the B/W goals. Change-Id: Ibe82db8718040513ae0d96366195d41001549189 Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
* msm: kgsl: Avoid L2PC on masked CPUsPrakash Kamliya2016-03-23
| | | | | | | | | | | | | | | If any of the Graphics rendering threads are running on masked CPUs, avoid L2PC for some duration on that CPU. This reduces latency on CPU (latency mainly because of L2 cache flush) and helps on performance. This change uses pm_qos_update_request_timeout() API. Add l2pc-cpu-mask property in device tree to enable this. CRs-Fixed: 962598 Change-Id: If90090cd2c68ea7c07e269723931fef7201ef136 Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* msm: kgsl: Fix direct references to HZSuman Tatiraju2016-03-23
| | | | | | | | Make the various timeout values HZ agnostic by using the proper macros and values instead. Change-Id: I708cd491f593782f0172cd7d2cca058cd41044a5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Add Qualcomm GPU driverJordan Crouse2016-03-22
| | | | | | | Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201."). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* dt-bindings: consolidate display related bindingsRob Herring2015-10-22
| | | | | | | | | | | | | | This is a quite large renaming to consolidate display related bindings into a single "display" directory from various scattered locations of video, drm, gpu, fb, mipi, and panel. The prior location was somewhat based on the Linux driver location, but bindings should be independent of that. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
* Merge tag 'drm/tegra/for-4.3-rc1' of ↵Dave Airlie2015-08-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.3-rc1 There are a bunch of non-critical fixes here that I've collected over the past few months, but the biggest part is Tegra210 support, in the DC, DSI and SOR/HDMI drivers. Also this finally restores DPMS with atomic mode-setting, something that has been broken since the conversion and which I had originally expected to take far less longer to fix. * tag 'drm/tegra/for-4.3-rc1' of git://anongit.freedesktop.org/tegra/linux: (41 commits) drm/tegra: sor: Add HDMI support drm/tegra: sor: Add Tegra210 eDP support drm/tegra: dc: Implement atomic DPMS drm/tegra: sor: Restore DPMS drm/tegra: dsi: Restore DPMS drm/tegra: hdmi: Restore DPMS drm/tegra: rgb: Restore DPMS drm/tegra: sor: Use DRM debugfs infrastructure for CRC drm/tegra: sor: Write correct head state registers drm/tegra: sor: Constify display mode drm/tegra: sor: Reset the correct debugfs fields drm/tegra: sor: Set minor after debugfs initialization drm/tegra: sor: Provide error messages in probe drm/tegra: sor: Rename registers for consistency drm/tegra: dpaux: Disable interrupt when detached drm/tegra: dpaux: Configure pads as I2C by default drm/tegra: dpaux: Provide error message in probe drm/tegra: dsi: Add Tegra210 support drm/tegra: dsi: Add Tegra132 support drm/tegra: dsi: Add Tegra124 support ...
| * drm/tegra: sor: Add HDMI supportThierry Reding2015-08-13
| | | | | | | | | | | | | | | | | | The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add HDMI support and name the debugfs node after the type of SOR. The SOR introduced with Tegra124 is known simply as "sor", whereas the additional SOR found on Tegra210 is known as "sor1". Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor: Add Tegra210 eDP supportThierry Reding2015-08-13
| | | | | | | | | | | | | | The SOR found on Tegra210 is very similar to the version found on Tegra124, except that it no longer supports LVDS. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm: sti: fix sub-components bindBenjamin Gaignard2015-08-03
|/ | | | | | | | | | | Fix misunderstanding in how use component framework. drm_platform_init() is now call only when all the sub-components are register themselves instead of the previous broken two stages mechanism. Update bindings documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
* Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2015-02-16
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "This is the main drm pull, it has a shared branch with some alsa crossover but everything should be acked by relevant people. New drivers: - ATMEL HLCDC driver - designware HDMI core support (used in multiple SoCs). core: - lots more atomic modesetting work, properties and atomic ioctl (hidden under option) - bridge rework allows support for Samsung exynos chromebooks to work finally. - some more panels supported i915: - atomic plane update support - DSI uses shared DSI infrastructure - Skylake basic support is all merged now - component framework used for i915/snd-hda interactions - write-combine cpu memory mappings - engine init code refactored - full ppgtt enabled where execlists are enabled. - cherryview rps/gpu turbo and pipe CRC support. radeon: - indirect draw support for evergreen/cayman - SMC and manual fan control for SI/CI - Displayport audio support amdkfd: - SDMA usermode queue support - replace suballocator usage with more suitable one - rework for allowing interfacing to more than radeon nouveau: - major renaming in prep for later splitting work - merge arm platform driver into nouveau - GK20A reclocking support msm: - conversion to atomic modesetting - YUV support for mdp4/5 - eDP support - hw cursor for mdp5 tegra: - conversion to atomic modesetting - better suspend/resume support for child devices rcar-du: - interlaced support imx: - move to using dw_hdmi shared support - mode_fixup support sti: - DVO support - HDMI infoframe support exynos: - refactoring and cleanup, removed lots of internal unnecessary abstraction - exynos7 DECON display controller support Along with the usual bunch of fixes, cleanups etc" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (724 commits) drm/radeon: fix voltage setup on hawaii drm/radeon/dp: Set EDP_CONFIGURATION_SET for bridge chips if necessary drm/radeon: only enable kv/kb dpm interrupts once v3 drm/radeon: workaround for CP HW bug on CIK drm/radeon: Don't try to enable write-combining without PAT drm/radeon: use 0-255 rather than 0-100 for pwm fan range drm/i915: Clamp efficient frequency to valid range drm/i915: Really ignore long HPD pulses on eDP drm/exynos: Add DECON driver drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL drm/i915: Insert a command barrier on BLT/BSD cache flushes drm/i915: Drop vblank wait from intel_dp_link_down drm/exynos: fix NULL pointer reference drm/exynos: remove exynos_plane_dpms drm/exynos: remove mode property of exynos crtc drm/exynos: Remove exynos_plane_dpms() call with no effect drm/i915: Squelch overzealous uncore reset WARN_ON drm/i915: Take runtime pm reference on hangcheck_info drm/i915: Correct the IOSF Dev_FN field for IOSF transfers drm/exynos: fix DMA_ATTR_NO_KERNEL_MAPPING usage ...
| * drm: sti: add DVO output connectorBenjamin Gaignard2014-12-30
| | | | | | | | | | | | | | | | | | Digital Video Out connector driver LCD panels. Like HDMI and HDA it create bridge, encoder and connector drm object. Add binding description. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
* | Documentation: DT bindings: add more Tegra chip compatible stringsPaul Walmsley2015-02-03
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
* drm: sti: add HQVDP planeBenjamin Gaignard2014-12-11
| | | | | | | | | | | | High Quality Video Data Plane is hardware IP dedicated to video rendering. Compare to GPD (graphic planes) it have better scaler capabilities. HQVDP use VID layer to push data into hardware compositor without going into DDR. From data flow point of view HQVDP and VID are nested so HQVPD update/disable VID. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
* drm: sti: remove gpio for HDMI hot plug detectionBenjamin Gaignard2014-12-11
| | | | | | | | gpio used for HDMI hot plug detection is useless, HDMI_STI register contains an hot plug detection status bit. Fix binding documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
* drm: sti: allow to change hdmi ddc i2c adapterBenjamin Gaignard2014-12-11
| | | | | | | Depending of the board configuration i2c for ddc could change, this patch allow to use a phandle to specify which i2c controller to use. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
* drm/tegra: dsi: Add ganged mode supportThierry Reding2014-11-13
| | | | | | | | | Implement ganged mode support for the Tegra DSI driver. The DSI host controller to gang up with is specified via a phandle in the device tree and the resolved DSI host controller used for the programming of the ganged-mode registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'dt-for-3.17' of ↵Linus Torvalds2014-08-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree changes from Olof Johansson: "Unlike the board branch, this keeps having large sets of changes for every release, but that's quite expected and is so far working well. Most of this is plumbing for various device bindings and new platforms, but there's also a bit of cleanup and code removal for things that are moved from platform code to DT contents (some OMAP clock code in particular). There's also a pinctrl driver for tegra here (appropriately acked), that's introduced this way to make it more bisectable. I'm happy to say that there were no conflicts at all with this branch this release, which means that changes are flowing through our tree as expected instead of merged through driver maintainers (or at least not done with conflicts). There are several new boards added, and a couple of SoCs. In no particular order: - Rockchip RK3288 SoC support, including DTS for a dev board that they have seeded with some community developers. - Better support for Hardkernel Exynos4-based ODROID boards. - CCF conversions (and dtsi contents) for several Renesas platforms. - Gumstix Pepper (TI AM335x) board support - TI eval board support for AM437x - Allwinner A23 SoC, very similar to existing ones which mostly has resulted in DT changes for support. Also includes support for an Ippo tablet with the chipset. - Allwinner A31 Hummingbird board support, not to be confused with the SolidRun i.MX-based Hummingboard. - Tegra30 Apalis board support" * tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits) ARM: dts: Enable USB host0 (EHCI) on rk3288-evb ARM: dts: add rk3288 ehci usb devices ARM: dts: Turn on USB host vbus on rk3288-evb ARM: tegra: apalis t30: fix device tree compatible node ARM: tegra: paz00: Fix some indentation inconsistencies ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: dts: rockchip: add watchdog node ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 ARM: dts: Add missing pinctrl for uart0/1 for exynos3250 ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250 ARM: dts: Add TMU dt node to monitor the temperature for exynos3250 ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250 ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only ARM: dts: max77686 is exynos5250-snow only ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table ARM: dts: Add PMU DT node for exynos5260 SoC ARM: EXYNOS: Add support for Exynos5410 PMU ARM: dts: Add PMU to exynos5410 ...
| * ARM: tegra: of: add GK20A device tree bindingAlexandre Courbot2014-07-17
| | | | | | | | | | | | | | | | Add the device tree binding documentation for the GK20A GPU used in Tegra K1 SoCs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | drm: sti: add bindings for DRM driverBenjamin Gaignard2014-07-30
|/ | | | | | | | Add DRM/KMS driver bindings documentation. Describe the required properties for each of the hardware IPs drivers. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
* drm/tegra: dsi - Implement VDD supply supportThierry Reding2014-06-05
| | | | | | | | | The DSI controllers are powered by a (typically 1.2V) regulator. Usually this is always on, so there was no need to support enabling or disabling it thus far. But in order not to consume any power when DSI is inactive, give the driver a chance to enable or disable the supply as needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-21 07:51:30 +0000