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* PM / devfreq: bimc-bwmon: Add support for version 4Rohit Gupta2016-09-14
| | | | | | | | | | | | The version 4 of the BIMC BWMON hardware now has provisions for counting bytes transferred at a high sampling rate. Modify the existing driver and governor algorithm to take advantage of that. Change-Id: I5080297aef7e310d5c1a19098c177ddecb729c25 Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> Signed-off-by: David Keitel <dkeitel@codeaurora.org>
* PM / devfreq: memlat: Add a core to memory frequency mapping tableRohit Gupta2016-08-17
| | | | | | | | | | | | | | | | | | | Add a core to memory frequency mapping table, which establishes a relationship between the core frequency and its corresponding bandwidth vote. The governor expects a "qcom,core-dev-table" table as part of a given memlat hardware monitor's device tree node. This table is read upon registration of the memlat governor. The table is then used to determine the memory bandwidth vote corresponding to the maximum of the core frequencies. CRs-Fixed: 1054146 Change-Id: I9df118da1433125b02c937bf1799a0944b110fac Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> Signed-off-by: David Keitel <dkeitel@codeaurora.org> Suggested-by: Saravana Kannan <skannan@codeaurora.org>
* dev_freq: devfreq_spdm: make cci_clk optional indicatorDavid Dai2016-06-29
| | | | | | | | | | Enable dev_freq SPDM support in order to increase BIMC vote based on bus rejection rate. Make cci_clk an optional property as it's not always a relevant indicator of cpu performance. CRs-Fixed: 1025515 Change-Id: I713cc396c8d563735981547e0dc18a63f6f15180 Signed-off-by: David Dai <daidavid1@codeaurora.org>
* PM / devfreq: memlat: Get complete CPU list during the probeRohit Gupta2016-03-23
| | | | | | | | | | | | | | | | | Currently arm-memlat-mon driver uses cpu_coregroup_mask to get the sibling CPUs for the first CPU specified during the probe. However if any of the CPUs in a cluster isn't hotplugged in even once before the probe runs then the call to cpu_coregroup_mask might not give the updated list of all the sibling CPUs for the specified CPU. With this change the initialization of the cpumask for the memlat device is obtained from the list of CPU phandles specified in the dtsi file. Change-Id: Ide97d60d9eecbbe1d33deda72a13951059822896 Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> [junjiew@codeaurora.org: dropped changes in dtsi files.] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq : Introduce a memory-latency governorRohit Gupta2016-03-23
| | | | | | | | | | | Use performance counters to detect the memory latency sensitivity of CPU workloads and vote for higher DDR frequency if required. Change-Id: Ie77a3523bc5713fc0315bd0abc3913f485a96e0e Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> Suggested-by: Saravana Kannan <skannan@codeaurora.org> [junjiew@codeaurora.org: dropped changes in arch/arm64/Kconfig] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: bw_hwmon: Expose a throttle adjust tunableRohit Gupta2016-03-23
| | | | | | | | | | | | | Newer versions of bimc-bwmon counters have the capability to fake higher byte count than what's actually transferred between a bus master and DDR if the bus master is being throttled by QoS hardware logic. Add support to set the throttle adjust field that comes with this newer version of bimc-bwmon. Change-Id: I33376c825fb11ab2e378f828b1d2ae46dd582836 Signed-off-by: Rohit Gupta <rohgup@codeaurora.org> [junjiew@codeaurora.org: dropped changes in dtsi.] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: msmcci-hwmon: Add support for handling shared irqHanumath Prasad2016-03-23
| | | | | | | | | | Some targets have a single irq line which is shared among all the cci hwmon counters. Enhance the driver to support shared interrupt handling. Change-Id: I5fdaecfaa14fa47e8f393fe51c538e5000e6ad5b Signed-off-by: Arun KS <arunks@codeaurora.org> Signed-off-by: Hanumath Prasad <hpprasad@codeaurora.org>
* devfreq: devfreq_simple_dev: Add support for preparing device clockJunjie Wu2016-03-23
| | | | | | | | | For certain implementation, device clock needs to be prepared before rate voting taking effect. Add support for preparing device clock during initialization. Change-Id: Ib22e83952187118342ff2546d4c79d3970a288f9 Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: Introduce M4M cache hwmon deviceJunjie Wu2016-03-23
| | | | | | | | | | Introduce M4M cache hwmon device to scale M4M based on hardware counter values. Change-Id: I6a1582e1e66ff3051fcf7f917efb959fe7af96ae Signed-off-by: Junjie Wu <junjiew@codeaurora.org> [junjiew@codeaurora.org: Dropped changes in arch/arm64/Kconfig] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: msmcci-hwmon: Add provision for normal reg accessArun KS2016-03-23
| | | | | | | | | On some systems, scm calls for cci registers are not supported. Use normal writel/readl in those cases. Add device tree flag to distinguish them. Change-Id: Icfb609d43f888856786c1881b2ee34ffd501e37a Signed-off-by: Arun KS <arunks@codeaurora.org>
* PM / devfreq: Introduce MSM CCI HWmon deviceJunjie Wu2016-03-23
| | | | | | | | | | | | | CCI400 on MSM has additional PMU counters that can be used to monitor cache requests. MSM CCI hardware monitor device configures these registers to monitor cache and inform governor. It can also set an IRQ when count exceeds a programmable limit. Change-Id: I1d80f57749b91c3972e60e54c75226c4d49d2ec6 Signed-off-by: Junjie Wu <junjiew@codeaurora.org> [junjiew@codeaurora.org: Dropped change in arch/arm64/Kconfig. Configuration should be selected directly in defconfig.] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: Add ARM PMU support for bw_hwmon governorJacob Stevens2016-03-23
| | | | | | | | | | The ARM PMU supports monitoring bus access from each CPU. It also has the ability to raise an IRQ when the counters overflow. This allows for it to be used with the bw_hwmon governor to scale the CPU BW requests by monitoring on the actual bus access traffic. Change-Id: I0594a6acb846acdc11a18744033636951f22e387 Signed-off-by: Jacob Stevens <jstevens@codeaurora.org>
* devfreq_devbw: Add support for voting for AB based on IBTaniya Das2016-03-23
| | | | | | | | | | | Some generic devfreq governors might not provide AB values since that's a devbw device specific attribute. In such cases, we might want to make an average bandwidth (AB) vote that's a percentage of the IB vote to make sure device BW requirement are not grossly misrepresented. This patch adds support for that. Change-Id: I76fbb8d688742058980f0d7568f2e7140023917e Signed-off-by: Taniya Das <tdas@codeaurora.org>
* devfreq: devfreq_spdm: Introduce devfreq_spdm driver.Dan Sneddon2016-03-23
| | | | | | | | | | | | | | | The devfreq_spdm driver implements support for bandwidth voting based on input from the SPDM device on MSM SoC's. The SPDM governor registers for the SPDM interrupt and then calls the hypervisor to determine the correct bandwidth to vote for. The devfreq framework poll timer is used to perdiocially ask the hypervisor for the new bandwidth to request from the MSM bus scaling code. Change-Id: I851457e40d49b5929f01c510249d3e6bb4ff2f1d Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org> [junjiew@codeaurora.org: resolved trivial conflicts] Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* PM / devfreq: bimc-bwmon: Add support for version 2Saravana Kannan2016-03-23
| | | | | | | | The version 2 of the BIMC BWMON HW doesn't reset the counter to 0 when it hits the threshold. It also has support for an overflow status register. Change-Id: I9f18d2153a2e5e762ec9950f26e0e7601468a80a Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
* PM / devfreq: Add MSM BIMC bwmon support for bw_hwmon governorSaravana Kannan2016-03-23
| | | | | | | | | | The BIMC bwmon device supports monitoring read/write traffic from each BIMC master port. It also has the capability to raise an IRQ when the traffic count exceeds a programmable threshold. This allows for it to be used with the bw_hwmon governor to scale the BW requests from each BIMC master. Change-Id: Ie8a1471226411e23954ed556292186a5a864ddc1 Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
* PM / devfreq: Add device tree binding documentationMatt Wagantall2016-03-23
| | | | | | | | Several devfreq drivers were added without their corresponding device tree bindings. Add them now. Change-Id: I4ca5073a6f3b16c3f02d65bb30f60361c353239f Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
* PM / devfreq: exynos-ppmu: Update documentation to support PPMUv2Chanwoo Choi2015-08-03
| | | | | | | | | | This patch updates the documentation to include the information of PPMUv2. The PPMUv2 is used for Exynos5433 and Exynos7420 to monitor the performance of each IP in Exynos SoC. Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
* PM / devfreq: event: Remove incorrect property in exynos-ppmu DT bindingJavier Martinez Canillas2015-08-03
| | | | | | | | | The exynos-ppmu driver is only a clock consumer and not a clock provider but its Device Tree binding listed #clock-cells as an optional property. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
* PM / devfreq: event: Add documentation for exynos-ppmu devfreq-event driverChanwoo Choi2015-01-30
This patch adds the documentation for Exynos PPMU (Platform Performance Monitoring Unit) devfreq-event driver. Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
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