diff options
Diffstat (limited to 'Documentation')
3 files changed, 34 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/spss_utils.txt b/Documentation/devicetree/bindings/arm/msm/spss_utils.txt new file mode 100644 index 000000000000..21b96377e5e4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/spss_utils.txt @@ -0,0 +1,27 @@ +Qualcomm Technologies, Inc. Secure Processor SubSystem Utilities (spss_utils) + +The Secure Processor SubSystem (SPSS) is a dedicated subsystem for security. +It has its own CPU, memories, and cryptographic engine. +It shall provide cryptographic services to other subsystems. +The SPSS firmware is loaded by PIL driver. +The communication with SPSS is done via spcom driver, using glink. + +The spss_utils driver selects the SPSS firmware file, +according to a dedicated fuse and the platform HW version. + +Required properties: +-compatible : should be "qcom,spss_utils" +-qcom,spss-fuse-addr: fuse register physical address +-qcom,spss-fuse-bit: fuse relevant bit +-qcom,spss-test-firmware-name: test firmware file name +-qcom,spss-prod-firmware-name: production firmware file name + +Example: + qcom,spss_utils { + compatible = "qcom,spss-utils"; + + qcom,spss-fuse-addr = <0x007841c4 0x4>; /* spss test fuse physical address */ + qcom,spss-fuse-bit = <27>; + qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/gt9xx/gt9xx.txt b/Documentation/devicetree/bindings/input/touchscreen/gt9xx/gt9xx.txt index af09840bb053..4051c2e70cc2 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/gt9xx/gt9xx.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/gt9xx/gt9xx.txt @@ -12,7 +12,7 @@ Required properties: - interrupt-parent : Parent of interrupt. - interrupts : Configuration of touch panel controller interrupt GPIO. - - goodix,family-id : Family identification of the controller. + - goodix,product-id : Product identification of the controller. - interrupt-gpios : Interrupt gpio which is to provide interrupts to host, same as "interrupts" node. - reset-gpios : Reset gpio to control the reset of chip. @@ -54,7 +54,7 @@ i2c@f9927000 { goodix,panel-coords = <0 0 720 1200>; goodix,display-coords = <0 0 720 1080>; goodix,button-map= <158 102 139>; - goodix,family-id = <0x0>; + goodix,product-id = "915"; goodix,cfg-data = [ 41 D0 02 00 05 0A 05 01 01 08 12 58 50 41 03 05 00 00 00 00 diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 48fdd3e03947..bceee5e1747d 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -13,6 +13,9 @@ Required properties: - reg : <registers mapping> first entry should contain UFS host controller register address space (mandatory), second entry is the device ref. clock control register map (optional). +- reset : reset specifier pair consists of phandle for the reset provider + and reset lines used by this controller. +- reset-names : reset signal name strings sorted in the same order as the resets property. Optional properties: - phys : phandle to UFS PHY node @@ -76,6 +79,8 @@ Example: clocks = <&core 0>, <&ref 0>, <&iface 0>; clock-names = "core_clk", "ref_clk", "iface_clk"; freq-table-hz = <100000000 200000000>, <0 0>, <0 0>; + resets = <clock_gcc GCC_UFS_BCR>; + reset-names = "core_reset"; phys = <&ufsphy1>; phy-names = "ufsphy"; rpm-level = <3>; |