diff options
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi | 89 |
1 files changed, 48 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi index 044bd1a5e510..a17fc360e2d0 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi @@ -420,65 +420,72 @@ vfe1-vdd-supply = <&gdsc_vfe1>; qcom,vdd-names = "camss-vdd", "vfe0-vdd", "vfe1-vdd"; - clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>, + qcom,clock-cntl-support; + clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csi0_clk_src>, - <&clock_mmss clk_mmss_camss_csi0_clk>, - <&clock_mmss clk_mmss_camss_csi0rdi_clk>, - <&clock_mmss clk_mmss_camss_csi0pix_clk>, <&clock_mmss clk_csi1_clk_src>, - <&clock_mmss clk_mmss_camss_csi1_clk>, - <&clock_mmss clk_mmss_camss_csi1rdi_clk>, - <&clock_mmss clk_mmss_camss_csi1pix_clk>, <&clock_mmss clk_csi2_clk_src>, - <&clock_mmss clk_mmss_camss_csi2_clk>, - <&clock_mmss clk_mmss_camss_csi2rdi_clk>, - <&clock_mmss clk_mmss_camss_csi2pix_clk>, <&clock_mmss clk_csi3_clk_src>, - <&clock_mmss clk_mmss_camss_csi3_clk>, + <&clock_mmss clk_mmss_camss_csi0rdi_clk>, + <&clock_mmss clk_mmss_camss_csi1rdi_clk>, + <&clock_mmss clk_mmss_camss_csi2rdi_clk>, <&clock_mmss clk_mmss_camss_csi3rdi_clk>, + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_csi2pix_clk>, <&clock_mmss clk_mmss_camss_csi3pix_clk>, - <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_csi3_clk>, <&clock_mmss clk_mmss_camss_vfe0_clk>, + <&clock_mmss clk_vfe0_clk_src>, <&clock_mmss clk_mmss_camss_csi_vfe0_clk>, - <&clock_mmss clk_vfe1_clk_src>, <&clock_mmss clk_mmss_camss_vfe1_clk>, + <&clock_mmss clk_vfe1_clk_src>, <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; - clock-names = "camss_top_ahb_clk", - "camss_ahb_clk", "ispif_ahb_clk", - "csi0_src_clk", "csi0_clk", - "csi0_pix_clk", "csi0_rdi_clk", - "csi1_src_clk", "csi1_clk", - "csi1_pix_clk", "csi1_rdi_clk", - "csi2_src_clk", "csi2_clk", - "csi2_pix_clk", "csi2_rdi_clk", - "csi3_src_clk", "csi3_clk", - "csi3_pix_clk", "csi3_rdi_clk", - "vfe0_clk_src", "camss_vfe_vfe0_clk", - "camss_csi_vfe0_clk", - "vfe1_clk_src", "camss_vfe_vfe1_clk", - "camss_csi_vfe1_clk"; - qcom,clock-rates = <0 0 0 + clock-names = "mnoc_maxi_clk", "mnoc_ahb_clk", + "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "camss_vfe_vfe0_clk", + "vfe0_clk_src", "camss_csi_vfe0_clk", + "camss_vfe_vfe1_clk", + "vfe1_clk_src", "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; - qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", - "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", - "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", - "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", - "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE"; - status = "disabled"; + qcom,clock-control = "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE"; + status = "ok"; }; vfe0: qcom,vfe0@ca10000 { |