diff options
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 31 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton-rumi.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton.dtsi | 31 |
4 files changed, 70 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index ab61ee115782..eed69d178fa3 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -137,3 +137,8 @@ vccq2-max-microamp = <600000>; qcom,disable-lpm; }; + +&clock_debug { + compatible = "qcom,dummycc"; + clock-output-names = "debug_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index ce6c5cf6c9b1..e444576b3eb2 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -884,7 +884,7 @@ }; clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon"; + compatible = "qcom,gcc-msmfalcon", "syscon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; @@ -922,6 +922,35 @@ #reset-cells = <1>; }; + cpu_debug: syscon@1791101c { + compatible = "syscon"; + reg = <0x1791101c 0x4>; + }; + + gpu_debug: syscon@05065120 { + compatible = "syscon"; + reg = <0x05065120 0x4>; + }; + + mmss_debug: syscon@c8c0900 { + compatible = "syscon"; + reg = <0xc8c0900 0x4>; + }; + + clock_debug: qcom,cc-debug@62000 { + compatible = "qcom,gcc-debug-msmfalcon"; + reg = <0x62000 0x4>; + reg-names = "dbg_offset"; + clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + qcom,cc-count = <4>; + qcom,gcc = <&clock_gcc>; + qcom,cpu = <&cpu_debug>; + qcom,mmss = <&mmss_debug>; + qcom,gpu = <&gpu_debug>; + #clock-cells = <1>; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdhci-msm-v5"; reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index 094d1ef6812c..faa474e60b8c 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -75,3 +75,8 @@ compatible = "qcom,dummycc"; clock-output-names = "mmss_clocks"; }; + +&clock_debug { + compatible = "qcom,dummycc"; + clock-output-names = "debug_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index e577a5692d90..20addf3ac9b9 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -561,7 +561,7 @@ }; clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon"; + compatible = "qcom,gcc-msmfalcon", "syscon"; reg = <0x100000 0x94000>; vdd_dig-supply = <&pm2falcon_s3_level>; vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; @@ -599,6 +599,35 @@ #reset-cells = <1>; }; + cpu_debug: syscon@1791101c { + compatible = "syscon"; + reg = <0x1791101c 0x4>; + }; + + gpu_debug: syscon@05065120 { + compatible = "syscon"; + reg = <0x05065120 0x4>; + }; + + mmss_debug: syscon@c8c0900 { + compatible = "syscon"; + reg = <0xc8c0900 0x4>; + }; + + clock_debug: qcom,cc-debug@62000 { + compatible = "qcom,gcc-debug-msmfalcon"; + reg = <0x62000 0x4>; + reg-names = "dbg_offset"; + clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + qcom,cc-count = <4>; + qcom,gcc = <&clock_gcc>; + qcom,cpu = <&cpu_debug>; + qcom,mmss = <&mmss_debug>; + qcom,gpu = <&gpu_debug>; + #clock-cells = <1>; + }; + qcom,ipc-spinlock@1f40000 { compatible = "qcom,ipc-spinlock-sfpb"; reg = <0x1f40000 0x8000>; |