diff options
61 files changed, 4449 insertions, 304 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt index d980ca89819a..7e421d3153db 100644 --- a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt +++ b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt @@ -64,10 +64,14 @@ Required properties: "qcom,gcc-mdm9607" "qcom,cc-debug-mdm9607" "qcom,gcc-cobalt" + "qcom,gcc-hamster" "qcom,cc-debug-cobalt" "qcom,gpucc-cobalt" "qcom,gfxcc-cobalt" + "qcom,gpucc-hamster" + "qcom,gfxcc-hamster" "qcom,mmsscc-cobalt" + "qcom,mmsscc-hamster" - reg: Pairs of physical base addresses and region sizes of memory mapped registers. diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index a2a57dfaa338..d05c3b8713c1 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -83,6 +83,9 @@ SoCs: - MSMCOBALT compatible = "qcom,msmcobalt" +- MSMHAMSTER + compatible = "qcom,msmhamster" + - MSM8952 compatible = "qcom,msm8952" @@ -239,6 +242,9 @@ compatible = "qcom,msm8996-mtp" compatible = "qcom,msm8996-adp" compatible = "qcom,msmcobalt-sim" compatible = "qcom,msmcobalt-rumi" +compatible = "qcom,msmhamster-rumi" +compatible = "qcom,msmhamster-cdp" +compatible = "qcom,msmhamster-mtp" compatible = "qcom,msm8952-rumi" compatible = "qcom,msm8952-sim" compatible = "qcom,msm8952-qrd" diff --git a/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt b/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt new file mode 100644 index 000000000000..901db5fb502d --- /dev/null +++ b/Documentation/devicetree/bindings/bluetooth/btfm_slim.txt @@ -0,0 +1,20 @@ +* BTFM Slimbus Slave Driver +BTFM Slimbus Slave driver configure and initialize slimbus slave device. +Bluetooth SCO and FM Audio data is transferred over slimbus interface. + +Required properties: + - compatible: Should be set to one of the following: + btfmslim_slave + - qcom,btfm-slim-ifd: BTFM slimbus slave device entry name + +Optional properties: + - qcom,btfm-slim-ifd-elemental-addr: BTFM slimbus slave device enumeration + address + +Example: + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msmhamster-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msmhamster-pinctrl.txt new file mode 100644 index 000000000000..6f3451618909 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msmhamster-pinctrl.txt @@ -0,0 +1,199 @@ +Qualcomm Technologies, Inc. MSMHAMSTER TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MSMHAMSTER platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,hamster-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio149, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data + sdc1_rclk, + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@01010000 { + compatible = "qcom,msmhamster-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 9f403c439395..f19ec55b027f 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -99,6 +99,8 @@ dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ msmcobalt-v2-mtp.dtb \ msmcobalt-v2-cdp.dtb +dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi index 48d5515ea450..9d39bedc2c23 100644 --- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi @@ -312,5 +312,29 @@ qcom,led-strings-list = [00 01 02 03]; qcom,en-ext-pfet-sc-pro; }; + + pmicobalt_haptics: qcom,haptic@c000 { + status = "disabled"; + compatible = "qcom,qpnp-haptic"; + reg = <0xc000 0x100>; + interrupts = <0x3 0xc0 0x0>, + <0x3 0xc0 0x1>; + interrupt-names = "sc-irq", "play-irq"; + qcom,actuator-type = "lra"; + qcom,play-mode = "direct"; + qcom,vmax-mv = <3200>; + qcom,ilim-ma = <800>; + qcom,wave-shape = "square"; + qcom,wave-play-rate-us = <6667>; + qcom,int-pwm-freq-khz = <505>; + qcom,sc-deb-cycles = <8>; + qcom,en-brake; + qcom,brake-pattern = [03 03 00 00]; + qcom,use-play-irq; + qcom,use-sc-irq; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi index 73db28c7c59b..f72dfacbc70d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi @@ -18,25 +18,29 @@ qca,bt-vdd-io-supply = <&pmcobalt_s3>; qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l25_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; - qca,bt-vdd-io-voltage-level = <1350000 1350000>; - qca,bt-vdd-xtal-voltage-level = <2050000 2050000>; + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; qca,bt-vdd-core-voltage-level = <1800000 1800000>; - qca,bt-vdd-ldo-voltage-level = <1300000 1300000>; - qca,bt-vdd-pa-voltage-level = <3300000 3300000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; qca,bt-chip-pwd-voltage-level = <3600000 3600000>; qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ }; }; +&blsp1_uart3_hs { + status = "ok"; +}; + &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; @@ -78,10 +82,16 @@ qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + cd-gpios = <&tlmm 95 0x1>; + status = "ok"; }; @@ -113,6 +123,10 @@ interrupts = <125 0x2008>; vdd-supply = <&pmcobalt_l6>; avdd-supply = <&pmcobalt_l28>; + synaptics,vdd-voltage = <1808000 1808000>; + synaptics,avdd-voltage = <3008000 3008000>; + synaptics,vdd-current = <40000>; + synaptics,avdd-current = <20000>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_suspend>; @@ -124,3 +138,7 @@ synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; }; }; + +&pmicobalt_haptics { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi index edde84c0ac71..7bae6848c61c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi @@ -18,25 +18,29 @@ qca,bt-vdd-io-supply = <&pmcobalt_s3>; qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l25_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; - qca,bt-vdd-io-voltage-level = <1350000 1350000>; - qca,bt-vdd-xtal-voltage-level = <2050000 2050000>; + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; qca,bt-vdd-core-voltage-level = <1800000 1800000>; - qca,bt-vdd-ldo-voltage-level = <1300000 1300000>; - qca,bt-vdd-pa-voltage-level = <3300000 3300000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; qca,bt-chip-pwd-voltage-level = <3600000 3600000>; qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ }; }; +&blsp1_uart3_hs { + status = "ok"; +}; + &ufsphy1 { vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; @@ -78,10 +82,16 @@ qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + cd-gpios = <&tlmm 95 0x1>; + status = "ok"; }; @@ -113,6 +123,10 @@ interrupts = <125 0x2008>; vdd-supply = <&pmcobalt_l6>; avdd-supply = <&pmcobalt_l28>; + synaptics,vdd-voltage = <1808000 1808000>; + synaptics,avdd-voltage = <3008000 3008000>; + synaptics,vdd-current = <40000>; + synaptics,avdd-current = <20000>; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_suspend>; @@ -124,3 +138,7 @@ synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; }; }; + +&pmicobalt_haptics { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi index 2af5ee78e4cb..03b8aa094796 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi @@ -1350,5 +1350,79 @@ }; }; }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi index 53a0360ff756..89134821899b 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi @@ -571,6 +571,15 @@ regulator-min-microvolt = <600000>; regulator-max-microvolt = <600000>; }; + + gfx_stub_vreg: regulator-gfx-stub { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_stub_corner"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + status = "disabled"; + }; }; &soc { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi index 5a8b2a3fc332..e0f3b09b4558 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi @@ -99,21 +99,21 @@ qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + cd-gpios = <&tlmm 95 0x1>; + status = "ok"; }; -/ { - gfx_stub_vreg: regulator-gfx-stub { - compatible = "qcom,stub-regulator"; - regulator-name = "gfx_stub_corner"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1>; - regulator-max-microvolt = <6>; - }; +&gfx_stub_vreg { + status = "okay"; }; &clock_gfx { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi index 06d9cde3b159..daa11686e921 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi @@ -54,21 +54,21 @@ qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + cd-gpios = <&tlmm 95 0x1>; + status = "ok"; }; -/ { - gfx_stub_vreg: regulator-gfx-stub { - compatible = "qcom,stub-regulator"; - regulator-name = "gfx_stub_corner"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1>; - regulator-max-microvolt = <6>; - }; +&gfx_stub_vreg { + status = "okay"; }; &clock_gfx { diff --git a/arch/arm/boot/dts/qcom/msmhamster-cdp.dts b/arch/arm/boot/dts/qcom/msmhamster-cdp.dts new file mode 100644 index 000000000000..dcb4b0830da3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmhamster-cdp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msmhamster.dtsi" +#include "msmcobalt-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM HAMSTER"; + compatible = "qcom,msmhamster-cdp", "qcom,msmhamster", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmhamster-mtp.dts b/arch/arm/boot/dts/qcom/msmhamster-mtp.dts new file mode 100644 index 000000000000..72106c97db40 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmhamster-mtp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msmhamster.dtsi" +#include "msmcobalt-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM HAMSTER"; + compatible = "qcom,msmhamster-mtp", "qcom,msmhamster", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmhamster-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmhamster-pinctrl.dtsi new file mode 100644 index 000000000000..5b0c41fd3d02 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmhamster-pinctrl.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03400000 { + compatible = "qcom,msmhamster-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8_a"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmhamster-rumi.dts b/arch/arm/boot/dts/qcom/msmhamster-rumi.dts new file mode 100644 index 000000000000..61118aaa2d68 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmhamster-rumi.dts @@ -0,0 +1,37 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "msmhamster.dtsi" +#include "msmcobalt-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM HAMSTER RUMI"; + compatible = "qcom,msmhamster-rumi", "qcom,msmhamster", "qcom,rumi"; + qcom,board-id = <15 0>; +}; + +&rpm_bus { + rpm-standalone; +}; + +&wdog { + status = "disabled"; +}; + +&gfx_stub_vreg { + regulator-max-microvolt = <8>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmhamster.dtsi b/arch/arm/boot/dts/qcom/msmhamster.dtsi new file mode 100644 index 000000000000..cf34ad20f84a --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmhamster.dtsi @@ -0,0 +1,60 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. Common device definitions should be placed inside the + * msmcobalt.dtsi file. + */ + +#include "msmcobalt-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM HAMSTER"; + qcom,msm-id = <306 0x0>; +}; + +&clock_gcc { + compatible = "qcom,gcc-hamster"; +}; + +&clock_mmss { + compatible = "qcom,mmsscc-hamster"; +}; + +&clock_gpu { + compatible = "qcom,gpucc-hamster"; +}; + +&clock_gfx { + compatible = "qcom,gfxcc-hamster"; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 185000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 285000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 358000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 434000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 542000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 630000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 185000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 285000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 358000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 434000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 542000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 630000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 559ac84dcaa2..f04c77bf1269 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -73,6 +73,14 @@ config ARCH_MSMCOBALT This enables support for the MSMCOBALT chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. +config ARCH_MSMHAMSTER + bool "Enable Support for Qualcomm Technologies Inc MSMHAMSTER" + depends on ARCH_QCOM + help + This enables support for the MSMHAMSTER chipset. + If you do not wish to build a kernel that runs + on this chipset,say 'N' here. + config ARCH_ROCKCHIP bool "Rockchip Platforms" select ARCH_HAS_RESET_CONTROLLER diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig index 508daf86e71a..5ccb0acbc231 100644 --- a/arch/arm64/configs/msm-perf_defconfig +++ b/arch/arm64/configs/msm-perf_defconfig @@ -218,6 +218,8 @@ CONFIG_BPF_JIT=y CONFIG_SOCKEV_NLMCAST=y CONFIG_BT=y CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_NET_9P=y diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig index e71d997a332e..d780a12b161c 100644 --- a/arch/arm64/configs/msm_defconfig +++ b/arch/arm64/configs/msm_defconfig @@ -220,6 +220,8 @@ CONFIG_BPF_JIT=y CONFIG_SOCKEV_NLMCAST=y CONFIG_BT=y CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_NET_9P=y @@ -536,6 +538,7 @@ CONFIG_MSM_SMP2P_TEST=y CONFIG_MSM_QMI_INTERFACE=y CONFIG_MSM_RPM_SMD=y CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y CONFIG_MSM_SYSMON_GLINK_COMM=y CONFIG_MSM_IPC_ROUTER_MHI_XPRT=y @@ -559,6 +562,7 @@ CONFIG_MSM_MPM_OF=y CONFIG_MSM_AVTIMER=y CONFIG_MSM_CORE_CTL_HELPER=y CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y CONFIG_MEM_SHARE_QMI_SERVICE=y CONFIG_MSM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index ec573f5ebbae..5134ffe9a6a0 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -48,6 +48,7 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y CONFIG_ARCH_MSMCOBALT=y +CONFIG_ARCH_MSMHAMSTER=y CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_HOST_GENERIC=y @@ -212,6 +213,8 @@ CONFIG_BPF_JIT=y CONFIG_SOCKEV_NLMCAST=y CONFIG_BT=y CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_NET_9P=y @@ -264,6 +267,10 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_UINPUT=y # CONFIG_SERIO_SERPORT is not set @@ -438,7 +445,6 @@ CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y CONFIG_MSM_GLINK_PKT=y CONFIG_MSM_SPM=y CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_XPU=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_ICNSS=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 29277d6ffdf8..4c851ce0168d 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -46,6 +46,7 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y CONFIG_ARCH_MSMCOBALT=y +CONFIG_ARCH_MSMHAMSTER=y CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_HOST_GENERIC=y @@ -211,6 +212,8 @@ CONFIG_BPF_JIT=y CONFIG_SOCKEV_NLMCAST=y CONFIG_BT=y CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_NET_9P=y @@ -265,6 +268,10 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y @@ -460,7 +467,6 @@ CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y CONFIG_MSM_GLINK_PKT=y CONFIG_MSM_SPM=y CONFIG_QCOM_SCM=y -CONFIG_QCOM_SCM_XPU=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_ICNSS=y @@ -518,6 +524,12 @@ CONFIG_DEBUG_INFO=y CONFIG_PAGE_OWNER=y CONFIG_MAGIC_SYSRQ=y CONFIG_SLUB_DEBUG_PANIC_ON=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_SLUB_DEBUG_ON=y CONFIG_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 @@ -526,12 +538,11 @@ CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_LOCKUP_DETECTOR=y CONFIG_PANIC_TIMEOUT=5 -# CONFIG_SCHED_DEBUG is not set CONFIG_PANIC_ON_SCHED_BUG=y CONFIG_PANIC_ON_RT_THROTTLING=y CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_ATOMIC_SLEEP=y @@ -550,6 +561,8 @@ CONFIG_BLK_DEV_IO_TRACE=y CONFIG_CPU_FREQ_SWITCH_PROFILER=y CONFIG_MEMTEST=y CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_ARM64_PTDUMP=y +CONFIG_PID_IN_CONTEXTIDR=y CONFIG_DEBUG_SET_MODULE_RONX=y CONFIG_DEBUG_RODATA=y CONFIG_FREE_PAGES_RDONLY=y diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 8e159f250026..1cf33c338ec8 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -104,6 +104,7 @@ static inline u64 gic_read_iar_common(void) asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); /* As per the architecture specification */ + isb(); mb(); return irqstat; } @@ -134,6 +135,7 @@ static inline void gic_write_pmr(u32 val) { asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); /* As per the architecture specification */ + isb(); mb(); } @@ -153,6 +155,7 @@ static inline void gic_write_sgi1r(u64 val) { asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); /* As per the architecture specification */ + isb(); mb(); } diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index 4478fb47b7a7..57b60eeb11c6 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -328,4 +328,24 @@ config MSM_BT_POWER Provides a parameter to switch on/off power from PMIC to Bluetooth device. +config BTFM_SLIM + tristate "MSM Bluetooth/FM Slimbus Driver" + depends on MSM_BT_POWER + help + This enables BT/FM slimbus driver to get multiple audio channel. + This will make use of slimbus platform driver and slimbus codec + driver to communicate with slimbus machine driver and LPSS which + is Slimbus master. + + Slimbus slave initialization and configuration will be done through + this driver. + +config BTFM_SLIM_WCN3990 + tristate "MSM Bluetooth/FM WCN3990 Device" + depends on BTFM_SLIM + help + This enables specific driver handle for WCN3990 device. + It is designed to adapt any future BT/FM device to implement a specific + chip initialization process and control. + endmenu diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index cde0ed5f8459..1151d0d17bf6 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -25,6 +25,10 @@ obj-$(CONFIG_BT_RTL) += btrtl.o obj-$(CONFIG_BT_QCA) += btqca.o obj-$(CONFIG_MSM_BT_POWER) += bluetooth-power.o +obj-$(CONFIG_BTFM_SLIM) += btfm_slim.o +obj-$(CONFIG_BTFM_SLIM) += btfm_slim_codec.o +obj-$(CONFIG_BTFM_SLIM_WCN3990) += btfm_slim_wcn3990.o + btmrvl-y := btmrvl_main.o btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o diff --git a/drivers/bluetooth/btfm_slim.c b/drivers/bluetooth/btfm_slim.c new file mode 100644 index 000000000000..73364de8a8bb --- /dev/null +++ b/drivers/bluetooth/btfm_slim.c @@ -0,0 +1,559 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/debugfs.h> +#include <linux/ratelimit.h> +#include <linux/slab.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> +#include <btfm_slim.h> +#include <btfm_slim_wcn3990.h> + +int btfm_slim_write(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src, uint8_t pgd) +{ + int ret, i; + struct slim_ele_access msg; + int slim_write_tries = SLIM_SLAVE_RW_MAX_TRIES; + + BTFMSLIM_DBG("Write to %s", pgd?"PGD":"IFD"); + msg.start_offset = SLIM_SLAVE_REG_OFFSET + reg; + msg.num_bytes = bytes; + msg.comp = NULL; + + for ( ; slim_write_tries != 0; slim_write_tries--) { + mutex_lock(&btfmslim->xfer_lock); + ret = slim_change_val_element(pgd ? btfmslim->slim_pgd : + &btfmslim->slim_ifd, &msg, src, bytes); + mutex_unlock(&btfmslim->xfer_lock); + if (ret == 0) + break; + usleep_range(5000, 5100); + } + + if (ret) { + BTFMSLIM_ERR("failed (%d)", ret); + return ret; + } + + for (i = 0; i < bytes; i++) + BTFMSLIM_DBG("Write 0x%02x to reg 0x%x", ((uint8_t *)src)[i], + reg + i); + return 0; +} + +int btfm_slim_write_pgd(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src) +{ + return btfm_slim_write(btfmslim, reg, bytes, src, PGD); +} + +int btfm_slim_write_inf(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src) +{ + return btfm_slim_write(btfmslim, reg, bytes, src, IFD); +} + +int btfm_slim_read(struct btfmslim *btfmslim, unsigned short reg, + int bytes, void *dest, uint8_t pgd) +{ + int ret, i; + struct slim_ele_access msg; + int slim_read_tries = SLIM_SLAVE_RW_MAX_TRIES; + + BTFMSLIM_DBG("Read from %s", pgd?"PGD":"IFD"); + msg.start_offset = SLIM_SLAVE_REG_OFFSET + reg; + msg.num_bytes = bytes; + msg.comp = NULL; + + for ( ; slim_read_tries != 0; slim_read_tries--) { + mutex_lock(&btfmslim->xfer_lock); + ret = slim_request_val_element(pgd ? btfmslim->slim_pgd : + &btfmslim->slim_ifd, &msg, dest, bytes); + mutex_unlock(&btfmslim->xfer_lock); + if (ret == 0) + break; + usleep_range(5000, 5100); + } + + if (ret) + BTFMSLIM_ERR("failed (%d)", ret); + + for (i = 0; i < bytes; i++) + BTFMSLIM_DBG("Read 0x%02x from reg 0x%x", ((uint8_t *)dest)[i], + reg + i); + + return 0; +} + +int btfm_slim_read_pgd(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest) +{ + return btfm_slim_read(btfmslim, reg, bytes, dest, PGD); +} + +int btfm_slim_read_inf(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest) +{ + return btfm_slim_read(btfmslim, reg, bytes, dest, IFD); +} + +int btfm_slim_enable_ch(struct btfmslim *btfmslim, struct btfmslim_ch *ch, + uint8_t rxport, uint32_t rates, uint8_t grp, uint8_t nchan) +{ + int ret, i; + struct slim_ch prop; + struct btfmslim_ch *chan = ch; + uint16_t ch_h[2]; + + if (!btfmslim || !ch) + return -EINVAL; + + BTFMSLIM_DBG("port:%d", ch->port); + + /* Define the channel with below parameters */ + prop.prot = SLIM_AUTO_ISO; + prop.baser = SLIM_RATE_4000HZ; + prop.dataf = SLIM_CH_DATAF_LPCM_AUDIO; + prop.auxf = SLIM_CH_AUXF_NOT_APPLICABLE; + prop.ratem = (rates/4000); + prop.sampleszbits = 16; + + ch_h[0] = ch->ch_hdl; + ch_h[1] = (grp) ? (ch+1)->ch_hdl : 0; + + ret = slim_define_ch(btfmslim->slim_pgd, &prop, ch_h, nchan, grp, + &ch->grph); + if (ret < 0) { + BTFMSLIM_ERR("slim_define_ch failed ret[%d]", ret); + goto error; + } + + for (i = 0; i < nchan; i++, ch++) { + /* Enable port through registration setting */ + if (btfmslim->vendor_port_en) { + ret = btfmslim->vendor_port_en(btfmslim, ch->port, + rxport, 1); + if (ret < 0) { + BTFMSLIM_ERR("vendor_port_en failed ret[%d]", + ret); + goto error; + } + } + + if (rxport) { + BTFMSLIM_INFO("slim_connect_sink(port: %d, ch: %d)", + ch->port, ch->ch); + /* Connect Port with channel given by Machine driver*/ + ret = slim_connect_sink(btfmslim->slim_pgd, + &ch->port_hdl, 1, ch->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_connect_sink failed ret[%d]", + ret); + goto remove_channel; + } + + } else { + BTFMSLIM_INFO("slim_connect_src(port: %d, ch: %d)", + ch->port, ch->ch); + /* Connect Port with channel given by Machine driver*/ + ret = slim_connect_src(btfmslim->slim_pgd, ch->port_hdl, + ch->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_connect_src failed ret[%d]", + ret); + goto remove_channel; + } + } + } + + /* Activate the channel immediately */ + BTFMSLIM_INFO( + "port: %d, ch: %d, grp: %d, ch->grph: 0x%x, ch_hdl: 0x%x", + chan->port, chan->ch, grp, chan->grph, chan->ch_hdl); + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? chan->grph : + chan->ch_hdl), SLIM_CH_ACTIVATE, true); + if (ret < 0) { + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + goto remove_channel; + } + +error: + return ret; + +remove_channel: + /* Remove the channel immediately*/ + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? ch->grph : ch->ch_hdl), + SLIM_CH_REMOVE, true); + if (ret < 0) + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + + return ret; +} + +int btfm_slim_disable_ch(struct btfmslim *btfmslim, struct btfmslim_ch *ch, + uint8_t rxport, uint8_t grp, uint8_t nchan) +{ + int ret, i; + + if (!btfmslim || !ch) + return -EINVAL; + + BTFMSLIM_INFO("port:%d, grp: %d, ch->grph:0x%x, ch->ch_hdl:0x%x ", + ch->port, grp, ch->grph, ch->ch_hdl); + /* Remove the channel immediately*/ + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? ch->grph : ch->ch_hdl), + SLIM_CH_REMOVE, true); + if (ret < 0) { + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + ret = slim_disconnect_ports(btfmslim->slim_pgd, + &ch->port_hdl, 1); + if (ret < 0) { + BTFMSLIM_ERR("slim_disconnect_ports failed ret[%d]", + ret); + goto error; + } + } + + /* Disable port through registration setting */ + for (i = 0; i < nchan; i++, ch++) { + if (btfmslim->vendor_port_en) { + ret = btfmslim->vendor_port_en(btfmslim, ch->port, + rxport, 0); + if (ret < 0) { + BTFMSLIM_ERR("vendor_port_en failed ret[%d]", + ret); + break; + } + } + } +error: + return ret; +} +static int btfm_slim_get_logical_addr(struct slim_device *slim) +{ + int ret = 0; + const unsigned long timeout = jiffies + + msecs_to_jiffies(SLIM_SLAVE_PRESENT_TIMEOUT); + + do { + ret = slim_get_logical_addr(slim, slim->e_addr, + ARRAY_SIZE(slim->e_addr), &slim->laddr); + if (!ret) { + BTFMSLIM_DBG("Assigned l-addr: 0x%x", slim->laddr); + break; + } + /* Give SLIMBUS time to report present and be ready. */ + usleep_range(1000, 1100); + BTFMSLIM_DBG("retyring get logical addr"); + } while (time_before(jiffies, timeout)); + + return ret; +} + +static int btfm_slim_alloc_port(struct btfmslim *btfmslim) +{ + int ret = -EINVAL, i; + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + if (!btfmslim) + return ret; + + rx_chs = btfmslim->rx_chs; + tx_chs = btfmslim->tx_chs; + + if (!rx_chs || !tx_chs) + return ret; + + BTFMSLIM_DBG("Rx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0 ; (rx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && + (i < BTFM_SLIM_NUM_CODEC_DAIS); i++, rx_chs++) { + + /* Get Rx port handler from slimbus driver based + * on port number + */ + ret = slim_get_slaveport(btfmslim->slim_pgd->laddr, + rx_chs->port, &rx_chs->port_hdl, SLIM_SINK); + if (ret < 0) { + BTFMSLIM_ERR("slave port failure port#%d - ret[%d]", + rx_chs->port, SLIM_SINK); + return ret; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", rx_chs->id, + rx_chs->name, rx_chs->port, rx_chs->port_hdl, + rx_chs->ch, rx_chs->ch_hdl); + } + + BTFMSLIM_DBG("Tx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (tx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && + (i < BTFM_SLIM_NUM_CODEC_DAIS); i++, tx_chs++) { + + /* Get Tx port handler from slimbus driver based + * on port number + */ + ret = slim_get_slaveport(btfmslim->slim_pgd->laddr, + tx_chs->port, &tx_chs->port_hdl, SLIM_SRC); + if (ret < 0) { + BTFMSLIM_ERR("slave port failure port#%d - ret[%d]", + tx_chs->port, SLIM_SRC); + return ret; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", tx_chs->id, + tx_chs->name, tx_chs->port, tx_chs->port_hdl, + tx_chs->ch, tx_chs->ch_hdl); + } + return ret; +} + +int btfm_slim_hw_init(struct btfmslim *btfmslim) +{ + int ret; + + BTFMSLIM_DBG(""); + if (!btfmslim) + return -EINVAL; + + if (btfmslim->enabled) { + BTFMSLIM_DBG("Already enabled"); + return 0; + } + mutex_lock(&btfmslim->io_lock); + + /* Assign Logical Address for PGD (Ported Generic Device) + * enumeration address + */ + ret = btfm_slim_get_logical_addr(btfmslim->slim_pgd); + if (ret) { + BTFMSLIM_ERR("failed to get slimbus %s logical address: %d", + btfmslim->slim_pgd->name, ret); + goto error; + } + + /* Assign Logical Address for Ported Generic Device + * enumeration address + */ + ret = btfm_slim_get_logical_addr(&btfmslim->slim_ifd); + if (ret) { + BTFMSLIM_ERR("failed to get slimbus %s logical address: %d", + btfmslim->slim_ifd.name, ret); + goto error; + } + + /* Allocate ports with logical address to get port handler from + * slimbus driver + */ + ret = btfm_slim_alloc_port(btfmslim); + if (ret) + goto error; + + /* Start vendor specific initialization and get port information */ + if (btfmslim->vendor_init) + ret = btfmslim->vendor_init(btfmslim); + + /* Only when all registers read/write successfully, it set to + * enabled status + */ + btfmslim->enabled = 1; +error: + mutex_unlock(&btfmslim->io_lock); + return ret; +} + + +int btfm_slim_hw_deinit(struct btfmslim *btfmslim) +{ + int ret = 0; + + if (!btfmslim) + return -EINVAL; + + if (!btfmslim->enabled) { + BTFMSLIM_DBG("Already disabled"); + return 0; + } + mutex_lock(&btfmslim->io_lock); + btfmslim->enabled = 0; + mutex_unlock(&btfmslim->io_lock); + return ret; +} + +static int btfm_slim_get_dt_info(struct btfmslim *btfmslim) +{ + int ret = 0; + struct slim_device *slim = btfmslim->slim_pgd; + struct slim_device *slim_ifd = &btfmslim->slim_ifd; + struct property *prop; + + if (!slim || !slim_ifd) + return -EINVAL; + + if (slim->dev.of_node) { + BTFMSLIM_DBG("Platform data from device tree (%s)", + slim->name); + ret = of_property_read_string(slim->dev.of_node, + "qcom,btfm-slim-ifd", &slim_ifd->name); + if (ret) { + BTFMSLIM_ERR("Looking up %s property in node %s failed", + "qcom,btfm-slim-ifd", + slim->dev.of_node->full_name); + return -ENODEV; + } + BTFMSLIM_DBG("qcom,btfm-slim-ifd (%s)", slim_ifd->name); + + prop = of_find_property(slim->dev.of_node, + "qcom,btfm-slim-ifd-elemental-addr", NULL); + if (!prop) { + BTFMSLIM_ERR("Looking up %s property in node %s failed", + "qcom,btfm-slim-ifd-elemental-addr", + slim->dev.of_node->full_name); + return -ENODEV; + } else if (prop->length != 6) { + BTFMSLIM_ERR( + "invalid codec slim ifd addr. addr length= %d", + prop->length); + return -ENODEV; + } + memcpy(slim_ifd->e_addr, prop->value, 6); + BTFMSLIM_DBG( + "PGD Enum Addr: %.02x:%.02x:%.02x:%.02x:%.02x: %.02x", + slim->e_addr[0], slim->e_addr[1], slim->e_addr[2], + slim->e_addr[3], slim->e_addr[4], slim->e_addr[5]); + BTFMSLIM_DBG( + "IFD Enum Addr: %.02x:%.02x:%.02x:%.02x:%.02x: %.02x", + slim_ifd->e_addr[0], slim_ifd->e_addr[1], + slim_ifd->e_addr[2], slim_ifd->e_addr[3], + slim_ifd->e_addr[4], slim_ifd->e_addr[5]); + } else { + BTFMSLIM_ERR("Platform data is not valid"); + } + + return ret; +} + +static int btfm_slim_probe(struct slim_device *slim) +{ + int ret = 0; + struct btfmslim *btfm_slim; + + BTFMSLIM_DBG(""); + if (!slim->ctrl) + return -EINVAL; + + /* Allocation btfmslim data pointer */ + btfm_slim = kzalloc(sizeof(struct btfmslim), GFP_KERNEL); + if (btfm_slim == NULL) { + BTFMSLIM_ERR("error, allocation failed"); + return -ENOMEM; + } + /* BTFM Slimbus driver control data configuration */ + btfm_slim->slim_pgd = slim; + + /* Assign vendor specific function */ + btfm_slim->rx_chs = SLIM_SLAVE_RXPORT; + btfm_slim->tx_chs = SLIM_SLAVE_TXPORT; + btfm_slim->vendor_init = SLIM_SLAVE_INIT; + btfm_slim->vendor_port_en = SLIM_SLAVE_PORT_EN; + + /* Created Mutex for slimbus data transfer */ + mutex_init(&btfm_slim->io_lock); + mutex_init(&btfm_slim->xfer_lock); + + /* Get Device tree node for Interface Device enumeration address */ + ret = btfm_slim_get_dt_info(btfm_slim); + if (ret) + goto dealloc; + + /* Add Interface Device for slimbus driver */ + ret = slim_add_device(btfm_slim->slim_pgd->ctrl, &btfm_slim->slim_ifd); + if (ret) { + BTFMSLIM_ERR("error, adding SLIMBUS device failed"); + goto dealloc; + } + + /* Platform driver data allocation */ + slim->dev.platform_data = btfm_slim; + + /* Driver specific data allocation */ + btfm_slim->dev = &slim->dev; + ret = btfm_slim_register_codec(&slim->dev); + return ret; + +dealloc: + mutex_destroy(&btfm_slim->io_lock); + mutex_destroy(&btfm_slim->xfer_lock); + kfree(btfm_slim); + return ret; +} +static int btfm_slim_remove(struct slim_device *slim) +{ + struct btfmslim *btfm_slim = slim->dev.platform_data; + + BTFMSLIM_DBG(""); + mutex_destroy(&btfm_slim->io_lock); + mutex_destroy(&btfm_slim->xfer_lock); + kfree(btfm_slim); + snd_soc_unregister_codec(&slim->dev); + + BTFMSLIM_DBG("slim_remove_device() - btfm_slim->slim_ifd"); + slim_remove_device(&btfm_slim->slim_ifd); + + BTFMSLIM_DBG("slim_remove_device() - btfm_slim->slim_pgd"); + slim_remove_device(slim); + return 0; +} + +static const struct slim_device_id btfm_slim_id[] = { + {SLIM_SLAVE_COMPATIBLE_STR, 0}, + {} +}; + +static struct slim_driver btfm_slim_driver = { + .driver = { + .name = "btfmslim-driver", + .owner = THIS_MODULE, + }, + .probe = btfm_slim_probe, + .remove = btfm_slim_remove, + .id_table = btfm_slim_id +}; + +static int __init btfm_slim_init(void) +{ + int ret; + + BTFMSLIM_DBG(""); + ret = slim_driver_register(&btfm_slim_driver); + if (ret) + BTFMSLIM_ERR("Failed to register slimbus driver: %d", ret); + return ret; +} + +static void __exit btfm_slim_exit(void) +{ + BTFMSLIM_DBG(""); + slim_driver_unregister(&btfm_slim_driver); +} + +module_init(btfm_slim_init); +module_exit(btfm_slim_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("BTFM Slimbus Slave driver"); diff --git a/drivers/bluetooth/btfm_slim.h b/drivers/bluetooth/btfm_slim.h new file mode 100644 index 000000000000..1161708d6a90 --- /dev/null +++ b/drivers/bluetooth/btfm_slim.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef BTFM_SLIM_H +#define BTFM_SLIM_H +#include <linux/slimbus/slimbus.h> + +#define BTFMSLIM_DBG(fmt, arg...) pr_debug("%s: " fmt "\n", __func__, ## arg) +#define BTFMSLIM_INFO(fmt, arg...) pr_info("%s: " fmt "\n", __func__, ## arg) +#define BTFMSLIM_ERR(fmt, arg...) pr_err("%s: " fmt "\n", __func__, ## arg) + +/* Vendor specific defines + * This should redefines in slimbus slave specific header +*/ +#define SLIM_SLAVE_COMPATIBLE_STR "btfmslim_slave" +#define SLIM_SLAVE_REG_OFFSET 0x0000 +#define SLIM_SLAVE_RXPORT NULL +#define SLIM_SLAVE_TXPORT NULL +#define SLIM_SLAVE_INIT NULL +#define SLIM_SLAVE_PORT_EN NULL + +/* Misc defines */ +#define SLIM_SLAVE_RW_MAX_TRIES 3 +#define SLIM_SLAVE_PRESENT_TIMEOUT 100 + +#define PGD 1 +#define IFD 0 + + +/* Codec driver defines */ +enum { + BTFM_FM_SLIM_TX = 0, + BTFM_BT_SCO_SLIM_TX, + BTFM_BT_SCO_SLIM_RX, + BTFM_BT_SPLIT_A2DP_SLIM_RX, + BTFM_SLIM_NUM_CODEC_DAIS +}; + +/* Slimbus Port defines - This should be redefined in specific device file */ +#define BTFM_SLIM_PGD_PORT_LAST 0xFF + +struct btfmslim_ch { + int id; + char *name; + uint32_t port_hdl; /* slimbus port handler */ + uint16_t port; /* slimbus port number */ + + uint8_t ch; /* slimbus channel number */ + uint16_t ch_hdl; /* slimbus channel handler */ + uint16_t grph; /* slimbus group channel handler */ +}; + +struct btfmslim { + struct device *dev; + struct slim_device *slim_pgd; + struct slim_device slim_ifd; + struct mutex io_lock; + struct mutex xfer_lock; + uint8_t enabled; + + uint32_t num_rx_port; + uint32_t num_tx_port; + + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + int (*vendor_init)(struct btfmslim *btfmslim); + int (*vendor_port_en)(struct btfmslim *btfmslim, uint8_t port_num, + uint8_t rxport, uint8_t enable); +}; + +/** + * btfm_slim_hw_init: Initialize slimbus slave device + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_hw_init(struct btfmslim *btfmslim); + +/** + * btfm_slim_hw_deinit: Deinitialize slimbus slave device + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_hw_deinit(struct btfmslim *btfmslim); + +/** + * btfm_slim_write: write value to pgd or ifd device + * @btfmslim: slimbus slave device data pointer. + * @reg: slimbus slave register address + * @bytes: length of data + * @src: data pointer to write + * @pgd: selection for device: either PGD or IFD + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_write(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src, uint8_t pgd); + + + +/** + * btfm_slim_read: read value from pgd or ifd device + * @btfmslim: slimbus slave device data pointer. + * @reg: slimbus slave register address + * @bytes: length of data + * @dest: data pointer to read + * @pgd: selection for device: either PGD or IFD + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_read(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest, uint8_t pgd); + + +/** + * btfm_slim_enable_ch: enable channel for slimbus slave port + * @btfmslim: slimbus slave device data pointer. + * @ch: slimbus slave channel pointer + * @rxport: rxport or txport + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_enable_ch(struct btfmslim *btfmslim, + struct btfmslim_ch *ch, uint8_t rxport, uint32_t rates, + uint8_t grp, uint8_t nchan); + +/** + * btfm_slim_disable_ch: disable channel for slimbus slave port + * @btfmslim: slimbus slave device data pointer. + * @ch: slimbus slave channel pointer + * @rxport: rxport or txport + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_disable_ch(struct btfmslim *btfmslim, + struct btfmslim_ch *ch, uint8_t rxport, uint8_t grp, uint8_t nchan); + +/** + * btfm_slim_register_codec: Register codec driver in slimbus device node + * @dev: device node + * Returns: + * -ENOMEM + * 0 +*/ +int btfm_slim_register_codec(struct device *dev); +#endif /* BTFM_SLIM_H */ diff --git a/drivers/bluetooth/btfm_slim_codec.c b/drivers/bluetooth/btfm_slim_codec.c new file mode 100644 index 000000000000..2194b8cc6f6f --- /dev/null +++ b/drivers/bluetooth/btfm_slim_codec.c @@ -0,0 +1,407 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/debugfs.h> +#include <linux/slimbus/slimbus.h> +#include <linux/ratelimit.h> +#include <linux/slab.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> +#include <btfm_slim.h> + +static int btfm_slim_codec_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + return 0; +} + +static unsigned int btfm_slim_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + return 0; +} + +static int btfm_slim_codec_probe(struct snd_soc_codec *codec) +{ + return 0; +} + +static int btfm_slim_codec_remove(struct snd_soc_codec *codec) +{ + return 0; +} + +static int btfm_slim_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret; + struct btfmslim *btfmslim = dai->dev->platform_data; + + BTFMSLIM_DBG("substream = %s stream = %d", + substream->name, substream->stream); + ret = btfm_slim_hw_init(btfmslim); + return ret; +} + +static void btfm_slim_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct btfmslim *btfmslim = dai->dev->platform_data; + + BTFMSLIM_DBG("substream = %s stream = %d", + substream->name, substream->stream); + btfm_slim_hw_deinit(btfmslim); +} + +static int btfm_slim_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + BTFMSLIM_DBG("dai_name = %s DAI-ID %x rate %d num_ch %d", + dai->name, dai->id, params_rate(params), + params_channels(params)); + + return 0; +} + +int btfm_slim_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int i, ret = -EINVAL; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch; + uint8_t rxport, grp = false, nchan = 1; + + BTFMSLIM_DBG("dai->name:%s, dai->id: %d, dai->rate: %d", dai->name, + dai->id, dai->rate); + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + grp = true; nchan = 2; + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_TX: + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + ch = btfmslim->rx_chs; + rxport = 1; + break; + case BTFM_SLIM_NUM_CODEC_DAIS: + default: + BTFMSLIM_ERR("dai->id is invalid:%d", dai->id); + return ret; + } + + /* Search for dai->id matched port handler */ + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != dai->id); ch++, i++) + ; + + if ((ch->port == BTFM_SLIM_PGD_PORT_LAST) || + (ch->id == BTFM_SLIM_NUM_CODEC_DAIS)) { + BTFMSLIM_ERR("ch is invalid!!"); + return ret; + } + + ret = btfm_slim_enable_ch(btfmslim, ch, rxport, dai->rate, grp, nchan); + return ret; +} + +int btfm_slim_dai_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int i, ret = -EINVAL; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch; + uint8_t rxport, grp = false, nchan = 1; + + BTFMSLIM_DBG("dai->name:%s, dai->id: %d, dai->rate: %d", dai->name, + dai->id, dai->rate); + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + grp = true; nchan = 2; + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_TX: + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + ch = btfmslim->rx_chs; + rxport = 1; + break; + case BTFM_SLIM_NUM_CODEC_DAIS: + default: + BTFMSLIM_ERR("dai->id is invalid:%d", dai->id); + return ret; + } + + /* Search for dai->id matched port handler */ + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != dai->id); ch++, i++) + ; + + if ((ch->port == BTFM_SLIM_PGD_PORT_LAST) || + (ch->id == BTFM_SLIM_NUM_CODEC_DAIS)) { + BTFMSLIM_ERR("ch is invalid!!"); + return ret; + } + ret = btfm_slim_disable_ch(btfmslim, ch, rxport, grp, nchan); + return ret; +} + +/* This function will be called once during boot up */ +static int btfm_slim_dai_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot) +{ + int ret = -EINVAL, i; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + BTFMSLIM_DBG(""); + + if (!btfmslim) + return ret; + + rx_chs = btfmslim->rx_chs; + tx_chs = btfmslim->tx_chs; + + if (!rx_chs || !tx_chs) + return ret; + + BTFMSLIM_DBG("Rx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (rx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && (i < rx_num); + i++, rx_chs++) { + /* Set Rx Channel number from machine driver and + * get channel handler from slimbus driver + */ + rx_chs->ch = *(uint8_t *)(rx_slot + i); + ret = slim_query_ch(btfmslim->slim_pgd, rx_chs->ch, + &rx_chs->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_query_ch failure ch#%d - ret[%d]", + rx_chs->ch, ret); + goto error; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", rx_chs->id, + rx_chs->name, rx_chs->port, rx_chs->port_hdl, + rx_chs->ch, rx_chs->ch_hdl); + } + + BTFMSLIM_DBG("Tx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (tx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && (i < tx_num); + i++, tx_chs++) { + /* Set Tx Channel number from machine driver and + * get channel handler from slimbus driver + */ + tx_chs->ch = *(uint8_t *)(tx_slot + i); + ret = slim_query_ch(btfmslim->slim_pgd, tx_chs->ch, + &tx_chs->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_query_ch failure ch#%d - ret[%d]", + tx_chs->ch, ret); + goto error; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", tx_chs->id, + tx_chs->name, tx_chs->port, tx_chs->port_hdl, + tx_chs->ch, tx_chs->ch_hdl); + } + +error: + return ret; +} + +static int btfm_slim_dai_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot) +{ + int i, ret = -EINVAL, *slot, j = 0, num = 1; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch; + + if (!btfmslim) + return ret; + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + num = 2; + case BTFM_BT_SCO_SLIM_TX: + if (!tx_slot || !tx_num) { + BTFMSLIM_ERR("Invalid tx_slot %p or tx_num %p", + tx_slot, tx_num); + return -EINVAL; + } + ch = btfmslim->tx_chs; + if (!ch) + return -EINVAL; + slot = tx_slot; + *rx_slot = 0; + *tx_num = num; + *rx_num = 0; + break; + case BTFM_BT_SCO_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + if (!rx_slot || !rx_num) { + BTFMSLIM_ERR("Invalid rx_slot %p or rx_num %p", + rx_slot, rx_num); + return -EINVAL; + } + ch = btfmslim->rx_chs; + if (!ch) + return -EINVAL; + slot = rx_slot; + *tx_slot = 0; + *tx_num = 0; + *rx_num = num; + break; + } + + do { + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && (ch->id != + BTFM_SLIM_NUM_CODEC_DAIS) && (ch->id != dai->id); + ch++, i++) + ; + + if (ch->id == BTFM_SLIM_NUM_CODEC_DAIS || + i == BTFM_SLIM_NUM_CODEC_DAIS) { + BTFMSLIM_ERR( + "No channel has been allocated for dai (%d)", + dai->id); + return -EINVAL; + } + + *(slot + j) = ch->ch; + BTFMSLIM_DBG("id:%d, port:%d, ch:%d, slot: %d", ch->id, + ch->port, ch->ch, *(slot + j)); + + /* In case it has mulitiple channels */ + if (++j < num) + ch++; + } while (j < num); + + return 0; +} + +static struct snd_soc_dai_ops btfmslim_dai_ops = { + .startup = btfm_slim_dai_startup, + .shutdown = btfm_slim_dai_shutdown, + .hw_params = btfm_slim_dai_hw_params, + .prepare = btfm_slim_dai_prepare, + .hw_free = btfm_slim_dai_hw_free, + .set_channel_map = btfm_slim_dai_set_channel_map, + .get_channel_map = btfm_slim_dai_get_channel_map, +}; + +static struct snd_soc_dai_driver btfmslim_dai[] = { + { /* FM Audio data multiple channel : FM -> qdsp */ + .name = "btfm_fm_slim_tx", + .id = BTFM_FM_SLIM_TX, + .capture = { + .stream_name = "FM TX Capture", + .rates = SNDRV_PCM_RATE_48000, /* 48 KHz */ + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 48000, + .rate_min = 48000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth SCO NBS voice uplink: bt -> modem */ + .name = "btfm_bt_sco_slim_tx", + .id = BTFM_BT_SCO_SLIM_TX, + .capture = { + .stream_name = "SCO TX Capture", + /* 8 KHz or 16 KHz */ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 16000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth SCO NBS voice downlink: modem -> bt */ + .name = "btfm_bt_sco_slim_rx", + .id = BTFM_BT_SCO_SLIM_RX, + .playback = { + .stream_name = "SCO RX Playback", + /* 8 KHz or 16 KHz */ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 16000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth Split A2DP data: qdsp -> bt */ + .name = "btfm_bt_split_a2dp_slim_rx", + .id = BTFM_BT_SPLIT_A2DP_SLIM_RX, + .playback = { + .stream_name = "SPLIT A2DP Playback", + .rates = SNDRV_PCM_RATE_48000, /* 48 KHz */ + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 48000, + .rate_min = 48000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, +}; + +static struct snd_soc_codec_driver btfmslim_codec = { + .probe = btfm_slim_codec_probe, + .remove = btfm_slim_codec_remove, + .read = btfm_slim_codec_read, + .write = btfm_slim_codec_write, +}; + +int btfm_slim_register_codec(struct device *dev) +{ + int ret = 0; + + BTFMSLIM_DBG(""); + /* Register Codec driver */ + ret = snd_soc_register_codec(dev, &btfmslim_codec, + btfmslim_dai, ARRAY_SIZE(btfmslim_dai)); + + if (ret) + BTFMSLIM_ERR("failed to register codec (%d)", ret); + + return ret; +} + +MODULE_DESCRIPTION("BTFM Slimbus Codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/bluetooth/btfm_slim_wcn3990.c b/drivers/bluetooth/btfm_slim_wcn3990.c new file mode 100644 index 000000000000..3300085be9a7 --- /dev/null +++ b/drivers/bluetooth/btfm_slim_wcn3990.c @@ -0,0 +1,130 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/slimbus/slimbus.h> +#include <btfm_slim.h> +#include <btfm_slim_wcn3990.h> + +/* WCN3990 Port assignment */ +struct btfmslim_ch wcn3990_rxport[] = { + {.id = BTFM_BT_SCO_SLIM_RX, .name = "SCO_Rx", + .port = CHRK_SB_PGD_PORT_RX_SCO}, + {.id = BTFM_BT_SPLIT_A2DP_SLIM_RX, .name = "A2P_Rx", + .port = CHRK_SB_PGD_PORT_RX_A2P}, + {.id = BTFM_SLIM_NUM_CODEC_DAIS, .name = "", + .port = BTFM_SLIM_PGD_PORT_LAST}, +}; + +struct btfmslim_ch wcn3990_txport[] = { + {.id = BTFM_FM_SLIM_TX, .name = "FM_Tx1", + .port = CHRK_SB_PGD_PORT_TX1_FM}, + {.id = BTFM_FM_SLIM_TX, .name = "FM_Tx2", + .port = CHRK_SB_PGD_PORT_TX2_FM}, + {.id = BTFM_BT_SCO_SLIM_TX, .name = "SCO_Tx", + .port = CHRK_SB_PGD_PORT_TX_SCO}, + {.id = BTFM_SLIM_NUM_CODEC_DAIS, .name = "", + .port = BTFM_SLIM_PGD_PORT_LAST}, +}; + +/* Function description */ +int btfm_slim_chrk_hw_init(struct btfmslim *btfmslim) +{ + int ret = 0; + uint8_t reg_val; + + BTFMSLIM_DBG(""); + + if (!btfmslim) + return -EINVAL; + + /* Get SB_SLAVE_HW_REV_MSB value*/ + ret = btfm_slim_read(btfmslim, CHRK_SB_SLAVE_HW_REV_MSB, 1, + ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to read (%d)", ret); + goto error; + } + BTFMSLIM_DBG("Major Rev: 0x%x, Minor Rev: 0x%x", + (reg_val & 0xF0) >> 4, (reg_val & 0x0F)); + + /* Get SB_SLAVE_HW_REV_LSB value*/ + ret = btfm_slim_read(btfmslim, CHRK_SB_SLAVE_HW_REV_LSB, 1, + ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to read (%d)", ret); + goto error; + } + BTFMSLIM_DBG("Step Rev: 0x%x", reg_val); + +error: + return ret; +} + + +int btfm_slim_chrk_enable_port(struct btfmslim *btfmslim, uint8_t port_num, + uint8_t rxport, uint8_t enable) +{ + int ret = 0; + uint8_t reg_val = 0; + uint16_t reg; + + BTFMSLIM_DBG("enable(%d)", enable); + if (rxport) { + /* Port enable */ + reg = CHRK_SB_PGD_PORT_RX_CFGN(port_num - 0x10); + } else { /* txport */ + /* Multiple Channel Setting - only FM Tx will be multiple + * channel + */ + if (enable && (port_num == CHRK_SB_PGD_PORT_TX1_FM || + port_num == CHRK_SB_PGD_PORT_TX2_FM)) { + + reg_val = (0x1 << CHRK_SB_PGD_PORT_TX1_FM) | + (0x1 << CHRK_SB_PGD_PORT_TX2_FM); + reg = CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_0(port_num); + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d)", ret); + goto error; + } + } + + /* Enable Tx port hw auto recovery for underrun or + * overrun error + */ + reg_val = (enable) ? (CHRK_ENABLE_OVERRUN_AUTO_RECOVERY | + CHRK_ENABLE_UNDERRUN_AUTO_RECOVERY) : 0x0; + + ret = btfm_slim_write(btfmslim, + CHRK_SB_PGD_PORT_TX_OR_UR_CFGN(port_num), 1, + ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d)", ret); + goto error; + } + + /* Port enable */ + reg = CHRK_SB_PGD_PORT_TX_CFGN(port_num); + } + + if (enable) + /* Set water mark to 1 and enable the port */ + reg_val = CHRK_SB_PGD_PORT_ENABLE | CHRK_SB_PGD_PORT_WM_LB; + else + reg_val = CHRK_SB_PGD_PORT_DISABLE; + + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) + BTFMSLIM_ERR("failed to write (%d)", ret); + +error: + return ret; +} diff --git a/drivers/bluetooth/btfm_slim_wcn3990.h b/drivers/bluetooth/btfm_slim_wcn3990.h new file mode 100644 index 000000000000..f6a260096c91 --- /dev/null +++ b/drivers/bluetooth/btfm_slim_wcn3990.h @@ -0,0 +1,140 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef BTFM_SLIM_WCN3990_H +#define BTFM_SLIM_WCN3990_H +#ifdef CONFIG_BTFM_SLIM_WCN3990 +#include <btfm_slim.h> + +/* Registers Address */ +#define CHRK_SB_COMP_TEST 0x00000000 +#define CHRK_SB_SLAVE_HW_REV_MSB 0x00000001 +#define CHRK_SB_SLAVE_HW_REV_LSB 0x00000002 +#define CHRK_SB_DEBUG_FEATURES 0x00000005 +#define CHRK_SB_INTF_INT_EN 0x00000010 +#define CHRK_SB_INTF_INT_STATUS 0x00000011 +#define CHRK_SB_INTF_INT_CLR 0x00000012 +#define CHRK_SB_FRM_CFG 0x00000013 +#define CHRK_SB_FRM_STATUS 0x00000014 +#define CHRK_SB_FRM_INT_EN 0x00000015 +#define CHRK_SB_FRM_INT_STATUS 0x00000016 +#define CHRK_SB_FRM_INT_CLR 0x00000017 +#define CHRK_SB_FRM_WAKEUP 0x00000018 +#define CHRK_SB_FRM_CLKCTL_DONE 0x00000019 +#define CHRK_SB_FRM_IE_STATUS 0x0000001A +#define CHRK_SB_FRM_VE_STATUS 0x0000001B +#define CHRK_SB_PGD_TX_CFG_STATUS 0x00000020 +#define CHRK_SB_PGD_RX_CFG_STATUS 0x00000021 +#define CHRK_SB_PGD_DEV_INT_EN 0x00000022 +#define CHRK_SB_PGD_DEV_INT_STATUS 0x00000023 +#define CHRK_SB_PGD_DEV_INT_CLR 0x00000024 +#define CHRK_SB_PGD_PORT_INT_EN_RX_0 0x00000030 +#define CHRK_SB_PGD_PORT_INT_EN_RX_1 0x00000031 +#define CHRK_SB_PGD_PORT_INT_EN_TX_0 0x00000032 +#define CHRK_SB_PGD_PORT_INT_EN_TX_1 0x00000033 +#define CHRK_SB_PGD_PORT_INT_STATUS_RX_0 0x00000034 +#define CHRK_SB_PGD_PORT_INT_STATUS_RX_1 0x00000035 +#define CHRK_SB_PGD_PORT_INT_STATUS_TX_0 0x00000036 +#define CHRK_SB_PGD_PORT_INT_STATUS_TX_1 0x00000037 +#define CHRK_SB_PGD_PORT_INT_CLR_RX_0 0x00000038 +#define CHRK_SB_PGD_PORT_INT_CLR_RX_1 0x00000039 +#define CHRK_SB_PGD_PORT_INT_CLR_TX_0 0x0000003A +#define CHRK_SB_PGD_PORT_INT_CLR_TX_1 0x0000003B +#define CHRK_SB_PGD_PORT_RX_CFGN(n) (0x00000040 + n) +#define CHRK_SB_PGD_PORT_TX_CFGN(n) (0x00000050 + n) +#define CHRK_SB_PGD_PORT_INT_RX_SOURCEN(n) (0x00000060 + n) +#define CHRK_SB_PGD_PORT_INT_TX_SOURCEN(n) (0x00000070 + n) +#define CHRK_SB_PGD_PORT_RX_STATUSN(n) (0x00000080 + n) +#define CHRK_SB_PGD_PORT_TX_STATUSN(n) (0x00000090 + n) +#define CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_0(n) (0x00000100 + 0x4*n) +#define CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_1(n) (0x00000101 + 0x4*n) +#define CHRK_SB_PGD_RX_PORTn_MULTI_CHNL_0(n) (0x00000180 + 0x4*n) +#define CHRK_SB_PGD_RX_PORTn_MULTI_CHNL_1(n) (0x00000181 + 0x4*n) +#define CHRK_SB_PGD_PORT_TX_OR_UR_CFGN(n) (0x000001F0 + n) + +/* Register Bit Setting */ +#define CHRK_ENABLE_OVERRUN_AUTO_RECOVERY (0x1 << 1) +#define CHRK_ENABLE_UNDERRUN_AUTO_RECOVERY (0x1 << 0) +#define CHRK_SB_PGD_PORT_ENABLE (0x1 << 0) +#define CHRK_SB_PGD_PORT_DISABLE (0x0 << 0) +#define CHRK_SB_PGD_PORT_WM_L1 (0x1 << 1) +#define CHRK_SB_PGD_PORT_WM_L2 (0x2 << 1) +#define CHRK_SB_PGD_PORT_WM_L3 (0x3 << 1) +#define CHRK_SB_PGD_PORT_WM_LB (0xB << 1) + +#define CHRK_SB_PGD_PORT_RX_NUM 16 +#define CHRK_SB_PGD_PORT_TX_NUM 16 + +/* PGD Port Map */ +#define CHRK_SB_PGD_PORT_TX_SCO 0 +#define CHRK_SB_PGD_PORT_TX1_FM 1 +#define CHRK_SB_PGD_PORT_TX2_FM 2 +#define CHRK_SB_PGD_PORT_RX_SCO 16 +#define CHRK_SB_PGD_PORT_RX_A2P 17 + + +/* Function Prototype */ + +/* + * btfm_slim_chrk_hw_init: Initialize wcn3990 specific slimbus slave device + * @btfmslim: slimbus slave device data pointer. + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_chrk_hw_init(struct btfmslim *btfmslim); + +/* + * btfm_slim_chrk_enable_rxport: Enable wcn3990 Rx port by given port number + * @btfmslim: slimbus slave device data pointer. + * @portNum: slimbus slave port number to enable + * @rxport: rxport or txport + * @enable: enable port or disable port + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_chrk_enable_port(struct btfmslim *btfmslim, uint8_t portNum, + uint8_t rxport, uint8_t enable); + +/* Specific defines for wcn3990 slimbus device */ +#define WCN3990_SLIM_REG_OFFSET 0x0800 + +#ifdef SLIM_SLAVE_REG_OFFSET +#undef SLIM_SLAVE_REG_OFFSET +#define SLIM_SLAVE_REG_OFFSET WCN3990_SLIM_REG_OFFSET +#endif + +/* Assign vendor specific function */ +extern struct btfmslim_ch wcn3990_txport[]; +extern struct btfmslim_ch wcn3990_rxport[]; + +#ifdef SLIM_SLAVE_RXPORT +#undef SLIM_SLAVE_RXPORT +#define SLIM_SLAVE_RXPORT (&wcn3990_rxport[0]) +#endif + +#ifdef SLIM_SLAVE_TXPORT +#undef SLIM_SLAVE_TXPORT +#define SLIM_SLAVE_TXPORT (&wcn3990_txport[0]) +#endif + +#ifdef SLIM_SLAVE_INIT +#undef SLIM_SLAVE_INIT +#define SLIM_SLAVE_INIT btfm_slim_chrk_hw_init +#endif + +#ifdef SLIM_SLAVE_PORT_EN +#undef SLIM_SLAVE_PORT_EN +#define SLIM_SLAVE_PORT_EN btfm_slim_chrk_enable_port +#endif +#endif /* CONFIG_BTFM_WCN3990 */ +#endif /* BTFM_SLIM_WCN3990_H */ diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index b74f7496955d..88d77977235d 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -2004,6 +2004,18 @@ static struct gate_clk gcc_ufs_rx_symbol_0_clk = { }, }; +static struct gate_clk gcc_ufs_rx_symbol_1_clk = { + .en_reg = GCC_UFS_RX_SYMBOL_1_CBCR, + .en_mask = BIT(0), + .delay_us = 500, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_ops_gate, + CLK_INIT(gcc_ufs_rx_symbol_1_clk.c), + }, +}; + static struct gate_clk gcc_ufs_tx_symbol_0_clk = { .en_reg = GCC_UFS_TX_SYMBOL_0_CBCR, .en_mask = BIT(0), @@ -2345,6 +2357,7 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ufs_ahb_clk.c, 0x00eb }, { &gcc_ufs_tx_symbol_0_clk.c, 0x00ec }, { &gcc_ufs_rx_symbol_0_clk.c, 0x00ed }, + { &gcc_ufs_rx_symbol_1_clk.c, 0x0162 }, { &gcc_ufs_unipro_core_clk.c, 0x00f0 }, { &gcc_ufs_ice_core_clk.c, 0x00f1 }, { &gcc_dcc_ahb_clk.c, 0x0119 }, @@ -2578,6 +2591,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_ufs_ice_core_clk), CLK_LIST(gcc_ufs_phy_aux_clk), CLK_LIST(gcc_ufs_rx_symbol_0_clk), + CLK_LIST(gcc_ufs_rx_symbol_1_clk), CLK_LIST(gcc_ufs_tx_symbol_0_clk), CLK_LIST(gcc_ufs_unipro_core_clk), CLK_LIST(gcc_usb30_master_clk), @@ -2611,6 +2625,7 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) struct resource *res; u32 regval; int ret; + bool is_vq = 0; ret = vote_bimc(&bimc_clk, INT_MAX); if (ret < 0) @@ -2659,6 +2674,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) if (ret < 0) return ret; + is_vq = of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-hamster"); + if (!is_vq) + gcc_ufs_rx_symbol_1_clk.c.ops = &clk_ops_dummy; + ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_cobalt, ARRAY_SIZE(msm_clocks_gcc_cobalt)); if (ret) @@ -2687,6 +2706,7 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) static struct of_device_id msm_clock_gcc_match_table[] = { { .compatible = "qcom,gcc-cobalt" }, + { .compatible = "qcom,gcc-hamster" }, {} }; diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-cobalt.c index e07fded0250b..c210f63c6bb4 100644 --- a/drivers/clk/msm/clock-gpu-cobalt.c +++ b/drivers/clk/msm/clock-gpu-cobalt.c @@ -39,6 +39,8 @@ static void __iomem *virt_base_gfx; #define gpucc_gpll0_source_val 5 #define gpu_pll0_pll_out_even_source_val 1 #define gpu_pll0_pll_out_odd_source_val 2 +#define gpu_pll1_pll_out_even_source_val 3 +#define gpu_pll1_pll_out_odd_source_val 4 #define SW_COLLAPSE_MASK BIT(0) #define GPU_CX_GDSCR_OFFSET 0x1004 @@ -107,8 +109,7 @@ static struct alpha_pll_clk gpu_pll0_pll = { .parent = &gpucc_xo.c, .dbg_name = "gpu_pll0_pll", .ops = &clk_ops_fabia_alpha_pll, - VDD_GPU_PLL_FMAX_MAP3(MIN, 252000000, LOWER, 504000000, - NOMINAL, 1300000500), + VDD_GPU_PLL_FMAX_MAP1(NOMINAL, 1300000500), CLK_INIT(gpu_pll0_pll.c), }, }; @@ -156,6 +157,65 @@ static struct div_clk gpu_pll0_pll_out_odd = { }, }; +static struct alpha_pll_clk gpu_pll1_pll = { + .masks = &pll_masks_p, + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL1_PLL_MODE, + .enable_config = 0x1, + .is_fabia = true, + .c = { + .rate = 0, + .parent = &gpucc_xo.c, + .dbg_name = "gpu_pll1_pll", + .ops = &clk_ops_fabia_alpha_pll, + VDD_GPU_PLL_FMAX_MAP1(NOMINAL, 1300000500), + CLK_INIT(gpu_pll1_pll.c), + }, +}; + +static struct div_clk gpu_pll1_pll_out_even = { + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL1_USER_CTL_MODE, + .mask = 0xf, + .shift = 8, + .data = { + .max_div = 8, + .min_div = 1, + .skip_odd_div = true, + .allow_div_one = true, + .rate_margin = 500, + }, + .ops = &postdiv_reg_ops, + .c = { + .parent = &gpu_pll1_pll.c, + .dbg_name = "gpu_pll1_pll_out_even", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gpu_pll1_pll_out_even.c), + }, +}; + +static struct div_clk gpu_pll1_pll_out_odd = { + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL0_USER_CTL_MODE, + .mask = 0xf, + .shift = 12, + .data = { + .max_div = 7, + .min_div = 3, + .skip_even_div = true, + .rate_margin = 500, + }, + .ops = &postdiv_reg_ops, + .c = { + .parent = &gpu_pll1_pll.c, + .dbg_name = "gpu_pll1_pll_out_odd", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gpu_pll1_pll_out_odd.c), + }, +}; + static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = { F_SLEW( 171000000, 342000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 251000000, 502000000, gpu_pll0_pll_out_even, 1, 0, 0), @@ -166,6 +226,18 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_gfx3d_clk_src_vq[] = { + F_SLEW( 185000000, 370000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 285000000, 570000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 358000000, 716000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 434000000, 868000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 542000000, 1084000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 630000000, 1260000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 670000000, 1340000000, gpu_pll1_pll_out_even, 1, 0, 0), + F_SLEW( 710000000, 1420000000, gpu_pll1_pll_out_even, 1, 0, 0), + F_END +}; + static struct rcg_clk gfx3d_clk_src = { .cmd_rcgr_reg = GPUCC_GFX3D_CMD_RCGR, .set_rate = set_rate_hid, @@ -407,6 +479,12 @@ static struct clk_lookup msm_clocks_gpucc_cobalt[] = { CLK_LIST(gpucc_gcc_dbg_clk), }; +static void msm_gpucc_hamster_fixup(void) +{ + gfx3d_isense_clk_src.c.ops = &clk_ops_dummy; + gpucc_gfx3d_isense_clk.c.ops = &clk_ops_dummy; +} + static struct platform_driver msm_clock_gfxcc_driver; int msm_gpucc_cobalt_probe(struct platform_device *pdev) { @@ -416,6 +494,7 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) struct regulator *reg; u32 regval; struct clk *tmp; + bool is_vq = 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); if (!res) { @@ -455,6 +534,11 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) regval &= ~BM(18, 17); writel_relaxed(regval, virt_base + gpucc_gcc_dbg_clk.offset); + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,gpucc-hamster"); + if (is_vq) + msm_gpucc_hamster_fixup(); + rc = of_msm_clock_register(of_node, msm_clocks_gpucc_cobalt, ARRAY_SIZE(msm_clocks_gpucc_cobalt)); if (rc) @@ -472,6 +556,7 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) static const struct of_device_id msm_clock_gpucc_match_table[] = { { .compatible = "qcom,gpucc-cobalt" }, + { .compatible = "qcom,gpucc-hamster" }, {}, }; @@ -488,12 +573,22 @@ static struct clk_lookup msm_clocks_gfxcc_cobalt[] = { CLK_LIST(gpu_pll0_pll), CLK_LIST(gpu_pll0_pll_out_even), CLK_LIST(gpu_pll0_pll_out_odd), + CLK_LIST(gpu_pll1_pll), + CLK_LIST(gpu_pll1_pll_out_even), + CLK_LIST(gpu_pll1_pll_out_odd), CLK_LIST(gfx3d_clk_src), CLK_LIST(gpucc_gfx3d_clk), CLK_LIST(gpucc_mx_clk), CLK_LIST(gfxcc_dbg_clk), }; +static void msm_gfxcc_hamster_fixup(void) +{ + gpu_pll0_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500; + gpu_pll1_pll.c.fmax[VDD_DIG_NOMINAL] = 1420000500; + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq; +} + int msm_gfxcc_cobalt_probe(struct platform_device *pdev) { struct resource *res; @@ -501,6 +596,7 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) int rc; struct regulator *reg; u32 regval; + bool is_vq = 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); if (!res) { @@ -552,13 +648,19 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) return rc; } + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,gfxcc-hamster"); + if (is_vq) + msm_gfxcc_hamster_fixup(); + + rc = of_msm_clock_register(of_node, msm_clocks_gfxcc_cobalt, ARRAY_SIZE(msm_clocks_gfxcc_cobalt)); if (rc) return rc; /* CRC ENABLE SEQUENCE */ - clk_set_rate(&gpucc_gfx3d_clk.c, 251000000); + clk_set_rate(&gpucc_gfx3d_clk.c, gfx3d_clk_src.c.fmax[2]); /* Turn on the GPU_CX GDSC */ regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET); regval &= ~SW_COLLAPSE_MASK; @@ -597,7 +699,8 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) writel_relaxed(0x00800000, virt_base_gfx + CRC_SID_FSM_OFFSET); /* Wait for 16 cycles before continuing */ udelay(1); - clk_set_rate(&gpucc_gfx3d_clk.c, 650000000); + clk_set_rate(&gpucc_gfx3d_clk.c, + gfx3d_clk_src.c.fmax[gfx3d_clk_src.c.num_fmax - 1]); /* Disable the graphics clock */ clk_disable_unprepare(&gpucc_gfx3d_clk.c); /* Turn off the gpu_cx and gpu_gx GDSCs */ @@ -622,6 +725,7 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) static const struct of_device_id msm_clock_gfxcc_match_table[] = { { .compatible = "qcom,gfxcc-cobalt" }, + { .compatible = "qcom,gfxcc-hamster" }, {}, }; diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c index 92e3921f590e..c060e0b20c24 100644 --- a/drivers/clk/msm/clock-mmss-cobalt.c +++ b/drivers/clk/msm/clock-mmss-cobalt.c @@ -240,6 +240,15 @@ static struct clk_freq_tbl ftbl_csi_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_csi_clk_src_vq[] = { + F_MM( 164571429, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + static struct rcg_clk csi0_clk_src = { .cmd_rcgr_reg = MMSS_CSI0_CMD_RCGR, .set_rate = set_rate_hid, @@ -265,6 +274,16 @@ static struct clk_freq_tbl ftbl_vfe_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_vfe_clk_src_vq[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + + static struct rcg_clk vfe0_clk_src = { .cmd_rcgr_reg = MMSS_VFE0_CMD_RCGR, .set_rate = set_rate_hid, @@ -298,8 +317,8 @@ static struct rcg_clk vfe1_clk_src = { static struct clk_freq_tbl ftbl_mdp_clk_src[] = { F_MM( 85714286, mmsscc_gpll0, 7, 0, 0), F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), - F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), F_MM( 150000000, mmsscc_gpll0, 4, 0, 0), + F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 275000000, mmpll5_pll_out, 3, 0, 0), F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), @@ -332,6 +351,16 @@ static struct clk_freq_tbl ftbl_maxi_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_maxi_clk_src_vq[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_MM( 75000000, mmsscc_gpll0_div, 4, 0, 0), + F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), + F_MM( 240000000, mmsscc_gpll0, 2.5, 0, 0), + F_MM( 323200000, mmpll0_pll_out, 2.5, 0, 0), + F_MM( 406000000, mmpll1_pll_out, 2, 0, 0), + F_END +}; + static struct rcg_clk maxi_clk_src = { .cmd_rcgr_reg = MMSS_MAXI_CMD_RCGR, .set_rate = set_rate_hid, @@ -355,6 +384,15 @@ static struct clk_freq_tbl ftbl_cpp_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_cpp_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + static struct rcg_clk cpp_clk_src = { .cmd_rcgr_reg = MMSS_CPP_CMD_RCGR, .set_rate = set_rate_hid, @@ -377,6 +415,14 @@ static struct clk_freq_tbl ftbl_jpeg0_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_jpeg0_clk_src_vq[] = { + F_MM( 75000000, mmsscc_gpll0, 8, 0, 0), + F_MM( 150000000, mmsscc_gpll0, 4, 0, 0), + F_MM( 320000000, mmpll7_pll_out, 3, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_END +}; + static struct rcg_clk jpeg0_clk_src = { .cmd_rcgr_reg = MMSS_JPEG0_CMD_RCGR, .set_rate = set_rate_hid, @@ -423,6 +469,16 @@ static struct clk_freq_tbl ftbl_video_core_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_video_core_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + static struct rcg_clk video_core_clk_src = { .cmd_rcgr_reg = MMSS_VIDEO_CORE_CMD_RCGR, .set_rate = set_rate_hid, @@ -445,6 +501,14 @@ static struct clk_freq_tbl ftbl_csiphy_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_csiphy_clk_src_vq[] = { + F_MM( 164570000, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_END +}; + static struct rcg_clk csiphy_clk_src = { .cmd_rcgr_reg = MMSS_CSIPHY_CMD_RCGR, .set_rate = set_rate_hid, @@ -512,6 +576,14 @@ static struct clk_freq_tbl ftbl_fd_core_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_fd_core_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 400000000, mmsscc_gpll0, 1.5, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + static struct rcg_clk fd_core_clk_src = { .cmd_rcgr_reg = MMSS_FD_CORE_CMD_RCGR, .set_rate = set_rate_hid, @@ -650,6 +722,16 @@ static struct clk_freq_tbl ftbl_video_subcore_clk_src[] = { F_END }; +static struct clk_freq_tbl ftbl_video_subcore_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + static struct rcg_clk video_subcore0_clk_src = { .cmd_rcgr_reg = MMSS_VIDEO_SUBCORE0_CMD_RCGR, .set_rate = set_rate_hid, @@ -765,8 +847,8 @@ static struct rcg_clk mclk0_clk_src = { .c = { .dbg_name = "mclk0_clk_src", .ops = &clk_ops_rcg_mnd, - VDD_DIG_FMAX_MAP3(LOWER, 33330000, LOW, 66670000, - NOMINAL, 68570000), + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), CLK_INIT(mclk0_clk_src.c), }, }; @@ -780,8 +862,8 @@ static struct rcg_clk mclk1_clk_src = { .c = { .dbg_name = "mclk1_clk_src", .ops = &clk_ops_rcg_mnd, - VDD_DIG_FMAX_MAP3(LOWER, 33330000, LOW, 66670000, - NOMINAL, 68570000), + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), CLK_INIT(mclk1_clk_src.c), }, }; @@ -795,8 +877,8 @@ static struct rcg_clk mclk2_clk_src = { .c = { .dbg_name = "mclk2_clk_src", .ops = &clk_ops_rcg_mnd, - VDD_DIG_FMAX_MAP3(LOWER, 33330000, LOW, 66670000, - NOMINAL, 68570000), + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), CLK_INIT(mclk2_clk_src.c), }, }; @@ -810,8 +892,8 @@ static struct rcg_clk mclk3_clk_src = { .c = { .dbg_name = "mclk3_clk_src", .ops = &clk_ops_rcg_mnd, - VDD_DIG_FMAX_MAP3(LOWER, 33330000, LOW, 66670000, - NOMINAL, 68570000), + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), CLK_INIT(mclk3_clk_src.c), }, }; @@ -832,7 +914,7 @@ static struct rcg_clk csi0phytimer_clk_src = { .dbg_name = "csi0phytimer_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, - NOMINAL, 269330000), + NOMINAL, 269333333), CLK_INIT(csi0phytimer_clk_src.c), }, }; @@ -847,7 +929,7 @@ static struct rcg_clk csi1phytimer_clk_src = { .dbg_name = "csi1phytimer_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, - NOMINAL, 269330000), + NOMINAL, 269333333), CLK_INIT(csi1phytimer_clk_src.c), }, }; @@ -862,7 +944,7 @@ static struct rcg_clk csi2phytimer_clk_src = { .dbg_name = "csi2phytimer_clk_src", .ops = &clk_ops_rcg, VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, - NOMINAL, 269330000), + NOMINAL, 269333333), CLK_INIT(csi2phytimer_clk_src.c), }, }; @@ -2379,6 +2461,87 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = { CLK_LIST(mmss_debug_mux), }; +static void msm_mmsscc_hamster_fixup(void) +{ + mmpll3_pll.c.rate = 1066000000; + mmpll3_pll.c.fmax[VDD_DIG_LOWER] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_LOW] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_LOW_L1] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_NOMINAL] = 1066000000; + mmpll3_pll.c.fmax[VDD_DIG_HIGH] = 1066000000; + + mmpll4_pll.c.fmax[VDD_DIG_LOW] = 384000000; + mmpll4_pll.c.fmax[VDD_DIG_LOW_L1] = 384000000; + mmpll4_pll.c.fmax[VDD_DIG_NOMINAL] = 768000000; + + mmpll5_pll.c.fmax[VDD_DIG_LOW] = 412500000; + mmpll5_pll.c.fmax[VDD_DIG_LOW_L1] = 412500000; + mmpll5_pll.c.fmax[VDD_DIG_NOMINAL] = 825000000; + + mmpll6_pll.c.rate = 888000000; + mmpll6_pll.c.fmax[VDD_DIG_LOWER] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_LOW] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_LOW_L1] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_NOMINAL] = 888000000; + mmpll6_pll.c.fmax[VDD_DIG_HIGH] = 888000000; + + vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_vq; + vfe0_clk_src.c.fmax[VDD_DIG_LOW] = 404000000; + vfe0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_vq; + vfe1_clk_src.c.fmax[VDD_DIG_LOW] = 404000000; + vfe1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + + csi0_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + csi1_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + csi2_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + csi3_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + + cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_vq; + cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + jpeg0_clk_src.freq_tbl = ftbl_jpeg0_clk_src_vq; + jpeg0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + csiphy_clk_src.freq_tbl = ftbl_csiphy_clk_src_vq; + csiphy_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + fd_core_clk_src.freq_tbl = ftbl_fd_core_clk_src_vq; + fd_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 400000000; + + csi0phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + csi1phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + csi2phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + + mdp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000; + extpclk_clk_src.c.fmax[VDD_DIG_LOW] = 312500000; + extpclk_clk_src.c.fmax[VDD_DIG_LOW_L1] = 375000000; + rot_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000; + + maxi_clk_src.freq_tbl = ftbl_maxi_clk_src_vq; + video_core_clk_src.freq_tbl = ftbl_video_core_clk_src_vq; + video_core_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_core_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000; + video_core_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_core_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; + + video_subcore0_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000; + video_subcore0_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_subcore0_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; + + video_subcore1_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000; + video_subcore1_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; +}; + int msm_mmsscc_cobalt_probe(struct platform_device *pdev) { struct resource *res; @@ -2386,6 +2549,7 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) struct clk *tmp; struct regulator *reg; u32 regval; + bool is_vq = 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); if (!res) { @@ -2446,6 +2610,11 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) ext_extpclk_clk_src.dev = &pdev->dev; ext_extpclk_clk_src.clk_id = "extpclk_src"; + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,mmsscc-hamster"); + if (is_vq) + msm_mmsscc_hamster_fixup(); + rc = of_msm_clock_register(pdev->dev.of_node, msm_clocks_mmss_cobalt, ARRAY_SIZE(msm_clocks_mmss_cobalt)); if (rc) @@ -2457,6 +2626,7 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) static struct of_device_id msm_clock_mmss_match_table[] = { { .compatible = "qcom,mmsscc-cobalt" }, + { .compatible = "qcom,mmsscc-hamster" }, {}, }; diff --git a/drivers/clk/msm/vdd-level-cobalt.h b/drivers/clk/msm/vdd-level-cobalt.h index e9c3e0adec6b..2cb40afafe3f 100644 --- a/drivers/clk/msm/vdd-level-cobalt.h +++ b/drivers/clk/msm/vdd-level-cobalt.h @@ -58,11 +58,10 @@ }, \ .num_fmax = VDD_DIG_NUM -#define VDD_GPU_PLL_FMAX_MAP2(l1, f1, l2, f2) \ +#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ .vdd_class = &vdd_gpucc_mx, \ .fmax = (unsigned long[VDD_DIG_NUM]) { \ [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ }, \ .num_fmax = VDD_DIG_NUM @@ -80,6 +79,7 @@ enum vdd_dig_levels { VDD_DIG_MIN, /* MIN SVS */ VDD_DIG_LOWER, /* SVS2 */ VDD_DIG_LOW, /* SVS */ + VDD_DIG_LOW_L1, /* SVSL1 */ VDD_DIG_NOMINAL, /* NOM */ VDD_DIG_HIGH, /* TURBO */ VDD_DIG_NUM @@ -90,6 +90,7 @@ static int vdd_corner[] = { RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ }; diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index d58645764c55..f9b5545519cb 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -1685,6 +1685,7 @@ static int _get_clocks(struct kgsl_device *device) const char *name; struct property *prop; + pwr->isense_clk_indx = 0; of_property_for_each_string(dev->of_node, "clock-names", prop, name) { int i; @@ -1703,6 +1704,8 @@ static int _get_clocks(struct kgsl_device *device) return ret; } + if (!strcmp(name, "isense_clk")) + pwr->isense_clk_indx = i; break; } } @@ -1785,6 +1788,10 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) clk_set_rate(pwr->grp_clks[6], clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ)); + if (pwr->isense_clk_indx) + clk_set_rate(pwr->grp_clks[pwr->isense_clk_indx], + KGSL_ISENSE_CLK_FREQ); + result = get_regulators(device); if (result) return result; diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index 13f0afb4f52c..7ed76760c043 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -36,6 +36,7 @@ #define KGSL_CONSTRAINT_PWR_MAXLEVELS 2 #define KGSL_RBBMTIMER_CLK_FREQ 19200000 +#define KGSL_ISENSE_CLK_FREQ 200000000 /* Symbolic table for the constraint type */ #define KGSL_CONSTRAINT_TYPES \ @@ -162,6 +163,7 @@ struct kgsl_pwrctrl { struct clk *grp_clks[KGSL_MAX_CLKS]; struct clk *dummy_mx_clk; struct clk *gpu_bimc_int_clk; + int isense_clk_indx; unsigned long power_flags; unsigned long ctrl_flags; struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS]; diff --git a/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c b/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c index 8e5064637f73..ea5d251c574f 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c +++ b/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c @@ -863,6 +863,11 @@ static int msm_eeprom_i2c_remove(struct i2c_client *client) return 0; } + if (!e_ctrl->eboard_info) { + pr_err("%s: eboard_info is NULL\n", __func__); + return 0; + } + msm_camera_put_clk_info(e_ctrl->pdev, &e_ctrl->eboard_info->power_info.clk_info, &e_ctrl->eboard_info->power_info.clk_ptr, diff --git a/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_qup_i2c.c b/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_qup_i2c.c index f542ec2e26bf..3b101798edac 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_qup_i2c.c +++ b/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_qup_i2c.c @@ -398,7 +398,7 @@ int32_t msm_camera_qup_i2c_poll(struct msm_camera_i2c_client *client, uint32_t addr, uint16_t data, enum msm_camera_i2c_data_type data_type, uint32_t delay_ms) { - int32_t rc; + int32_t rc = 0; int i; S_I2C_DBG("%s: addr: 0x%x data: 0x%x dt: %d\n", __func__, addr, data, data_type); diff --git a/drivers/pinctrl/qcom/pinctrl-msmhamster.c b/drivers/pinctrl/qcom/pinctrl-msmhamster.c new file mode 100644 index 000000000000..935e5e324a75 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msmhamster.c @@ -0,0 +1,1905 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) ( \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + }) + +#define NORTH 0x500000 +#define WEST 0x100000 +#define EAST 0x900000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msmhamster_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; + +enum msmhamster_functions { + msm_mux_blsp_spi1, + msm_mux_blsp_uim1_a, + msm_mux_blsp_uart1_a, + msm_mux_blsp_i2c1, + msm_mux_blsp_spi8, + msm_mux_blsp_uart8_a, + msm_mux_blsp_uim8_a, + msm_mux_qdss_cti0_b, + msm_mux_blsp_i2c8, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1_b, + msm_mux_blsp_uim1_b, + msm_mux_wlan1_adc1, + msm_mux_atest_usb13, + msm_mux_bimc_dte1, + msm_mux_tsif1_sync, + msm_mux_wlan1_adc0, + msm_mux_atest_usb12, + msm_mux_bimc_dte0, + msm_mux_mdp_vsync_a, + msm_mux_blsp_i2c4, + msm_mux_atest_gpsadc1, + msm_mux_wlan2_adc1, + msm_mux_atest_usb11, + msm_mux_edp_lcd, + msm_mux_dbg_out, + msm_mux_atest_gpsadc0, + msm_mux_wlan2_adc0, + msm_mux_atest_usb10, + msm_mux_mdp_vsync, + msm_mux_m_voc, + msm_mux_cam_mclk, + msm_mux_pll_bypassnl, + msm_mux_qdss_gpio0, + msm_mux_pll_reset, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_cci_i2c, + msm_mux_qdss_gpio4, + msm_mux_phase_flag14, + msm_mux_qdss_gpio5, + msm_mux_phase_flag15, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_cci_timer4, + msm_mux_blsp2_spi, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_cci_timer0, + msm_mux_qdss_gpio8, + msm_mux_vsense_data0, + msm_mux_cci_timer1, + msm_mux_qdss_gpio, + msm_mux_vsense_data1, + msm_mux_cci_timer2, + msm_mux_blsp1_spi_b, + msm_mux_qdss_gpio9, + msm_mux_vsense_mode, + msm_mux_cci_timer3, + msm_mux_cci_async, + msm_mux_blsp1_spi_a, + msm_mux_qdss_gpio10, + msm_mux_vsense_clkout, + msm_mux_hdmi_rcv, + msm_mux_hdmi_cec, + msm_mux_blsp_spi2, + msm_mux_blsp_uart2_a, + msm_mux_blsp_uim2_a, + msm_mux_pwr_modem, + msm_mux_hdmi_ddc, + msm_mux_blsp_i2c2, + msm_mux_pwr_nav, + msm_mux_pwr_crypto, + msm_mux_hdmi_hot, + msm_mux_edp_hot, + msm_mux_pci_e0, + msm_mux_jitter_bist, + msm_mux_agera_pll, + msm_mux_atest_tsens, + msm_mux_usb_phy, + msm_mux_lpass_slimbus, + msm_mux_sd_write, + msm_mux_tsif1_error, + msm_mux_blsp_spi6, + msm_mux_blsp_uart3_b, + msm_mux_blsp_uim3_b, + msm_mux_blsp_i2c6, + msm_mux_bt_reset, + msm_mux_blsp_spi3, + msm_mux_blsp_uart3_a, + msm_mux_blsp_uim3_a, + msm_mux_blsp_i2c3, + msm_mux_blsp_spi9, + msm_mux_blsp_uart9_a, + msm_mux_blsp_uim9_a, + msm_mux_blsp10_spi_b, + msm_mux_qdss_cti0_a, + msm_mux_blsp_i2c9, + msm_mux_blsp10_spi_a, + msm_mux_blsp_spi7, + msm_mux_blsp_uart7_a, + msm_mux_blsp_uim7_a, + msm_mux_blsp_i2c7, + msm_mux_qua_mi2s, + msm_mux_blsp10_spi, + msm_mux_gcc_gp1_a, + msm_mux_ssc_irq, + msm_mux_blsp_spi11, + msm_mux_blsp_uart8_b, + msm_mux_blsp_uim8_b, + msm_mux_gcc_gp2_a, + msm_mux_qdss_cti1_a, + msm_mux_gcc_gp3_a, + msm_mux_blsp_i2c11, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng, + msm_mux_pri_mi2s, + msm_mux_sp_cmu, + msm_mux_blsp_spi10, + msm_mux_blsp_uart7_b, + msm_mux_blsp_uim7_b, + msm_mux_pri_mi2s_ws, + msm_mux_blsp_i2c10, + msm_mux_spkr_i2s, + msm_mux_audio_ref, + msm_mux_blsp9_spi, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_btfm_slimbus, + msm_mux_phase_flag0, + msm_mux_ter_mi2s, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_phase_flag9, + msm_mux_phase_flag4, + msm_mux_gcc_gp1_b, + msm_mux_sec_mi2s, + msm_mux_blsp_spi12, + msm_mux_blsp_uart9_b, + msm_mux_blsp_uim9_b, + msm_mux_gcc_gp2_b, + msm_mux_gcc_gp3_b, + msm_mux_blsp_i2c12, + msm_mux_blsp_spi5, + msm_mux_blsp_uart2_b, + msm_mux_blsp_uim2_b, + msm_mux_blsp_i2c5, + msm_mux_tsif1_clk, + msm_mux_phase_flag10, + msm_mux_tsif1_en, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_blsp1_spi, + msm_mux_tgu_ch0, + msm_mux_qdss_cti1_b, + msm_mux_tsif1_data, + msm_mux_sdc4_cmd, + msm_mux_tgu_ch1, + msm_mux_phase_flag1, + msm_mux_tsif2_error, + msm_mux_sdc43, + msm_mux_vfr_1, + msm_mux_phase_flag2, + msm_mux_tsif2_clk, + msm_mux_sdc4_clk, + msm_mux_tsif2_en, + msm_mux_sdc42, + msm_mux_sd_card, + msm_mux_tsif2_data, + msm_mux_sdc41, + msm_mux_tsif2_sync, + msm_mux_sdc40, + msm_mux_phase_flag3, + msm_mux_mdp_vsync_b, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_blsp_uart8, + msm_mux_blsp11_i2c, + msm_mux_prng_rosc, + msm_mux_phase_flag5, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim_batt, + msm_mux_phase_flag16, + msm_mux_nav_dr, + msm_mux_phase_flag11, + msm_mux_phase_flag12, + msm_mux_phase_flag13, + msm_mux_atest_char, + msm_mux_adsp_ext, + msm_mux_phase_flag17, + msm_mux_atest_char3, + msm_mux_phase_flag18, + msm_mux_atest_char2, + msm_mux_phase_flag19, + msm_mux_atest_char1, + msm_mux_phase_flag20, + msm_mux_atest_char0, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_phase_flag23, + msm_mux_phase_flag24, + msm_mux_phase_flag25, + msm_mux_modem_tsync, + msm_mux_nav_pps, + msm_mux_phase_flag26, + msm_mux_phase_flag27, + msm_mux_qlink_request, + msm_mux_phase_flag28, + msm_mux_qlink_enable, + msm_mux_phase_flag6, + msm_mux_phase_flag29, + msm_mux_phase_flag30, + msm_mux_phase_flag31, + msm_mux_pa_indicator, + msm_mux_ssbi1, + msm_mux_isense_dbg, + msm_mux_mss_lte, + msm_mux_gpio, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_uim1_a_groups[] = { + "gpio0", "gpio1", +}; +static const char * const blsp_uart1_a_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_spi8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart8_a_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim8_a_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qdss_cti0_b_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const blsp_spi4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart1_b_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uim1_b_groups[] = { + "gpio8", "gpio9", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const tsif1_sync_groups[] = { + "gpio9", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const mdp_vsync_a_groups[] = { + "gpio10", "gpio11", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio10", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const mdp_vsync_groups[] = { + "gpio12", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio13", "gpio117", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio14", "gpio118", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio15", "gpio119", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio16", "gpio120", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio17", "gpio121", +}; +static const char * const phase_flag14_groups[] = { + "gpio18", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio18", "gpio122", +}; +static const char * const phase_flag15_groups[] = { + "gpio19", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio19", "gpio41", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio20", "gpio42", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const blsp2_spi_groups[] = { + "gpio25", "gpio29", "gpio30", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio25", "gpio79", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio26", "gpio80", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio27", "gpio93", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio28", "gpio43", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio29", "gpio44", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio21", "gpio75", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const qdss_gpio_groups[] = { + "gpio22", "gpio30", "gpio123", "gpio124", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const blsp1_spi_b_groups[] = { + "gpio23", "gpio28", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio23", "gpio76", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const blsp1_spi_a_groups[] = { + "gpio24", "gpio27", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio24", "gpio77", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const hdmi_rcv_groups[] = { + "gpio30", +}; +static const char * const hdmi_cec_groups[] = { + "gpio31", +}; +static const char * const blsp_spi2_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const blsp_uart2_a_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const blsp_uim2_a_groups[] = { + "gpio31", "gpio34", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio32", "gpio33", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const hdmi_hot_groups[] = { + "gpio34", +}; +static const char * const edp_hot_groups[] = { + "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", "gpio37", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const agera_pll_groups[] = { + "gpio36", "gpio37", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", "gpio70", "gpio71", "gpio72", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const blsp_spi6_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uart3_b_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uim3_b_groups[] = { + "gpio41", "gpio42", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio43", "gpio44", +}; +static const char * const bt_reset_groups[] = { + "gpio45", +}; +static const char * const blsp_spi3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uart3_a_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uim3_a_groups[] = { + "gpio45", "gpio46", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio47", "gpio48", +}; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uart9_a_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uim9_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp10_spi_b_groups[] = { + "gpio49", "gpio50", +}; +static const char * const qdss_cti0_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp_i2c9_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp10_spi_a_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp_spi7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uart7_a_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uim7_a_groups[] = { + "gpio53", "gpio54", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const blsp10_spi_groups[] = { + "gpio57", +}; +static const char * const gcc_gp1_a_groups[] = { + "gpio57", +}; +static const char * const ssc_irq_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78", + "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; +static const char * const blsp_spi11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uart8_b_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uim8_b_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp2_a_groups[] = { + "gpio58", +}; +static const char * const qdss_cti1_a_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp3_a_groups[] = { + "gpio59", +}; +static const char * const blsp_i2c11_groups[] = { + "gpio60", "gpio61", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio67", "gpio68", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const blsp_spi10_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uart7_b_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uim7_b_groups[] = { + "gpio65", "gpio66", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const blsp_i2c10_groups[] = { + "gpio67", "gpio68", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const blsp9_spi_groups[] = { + "gpio70", "gpio71", "gpio72", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const phase_flag0_groups[] = { + "gpio73", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const phase_flag7_groups[] = { + "gpio74", +}; +static const char * const phase_flag8_groups[] = { + "gpio75", +}; +static const char * const phase_flag9_groups[] = { + "gpio76", +}; +static const char * const phase_flag4_groups[] = { + "gpio77", +}; +static const char * const gcc_gp1_b_groups[] = { + "gpio78", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const blsp_spi12_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uart9_b_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uim9_b_groups[] = { + "gpio81", "gpio82", +}; +static const char * const gcc_gp2_b_groups[] = { + "gpio81", +}; +static const char * const gcc_gp3_b_groups[] = { + "gpio82", +}; +static const char * const blsp_i2c12_groups[] = { + "gpio83", "gpio84", +}; +static const char * const blsp_spi5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uart2_b_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uim2_b_groups[] = { + "gpio85", "gpio86", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio87", "gpio88", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const phase_flag10_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const blsp1_spi_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const qdss_cti1_b_groups[] = { + "gpio90", "gpio91", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const phase_flag1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const sdc43_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const phase_flag2_groups[] = { + "gpio92", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const sdc42_groups[] = { + "gpio94", +}; +static const char * const sd_card_groups[] = { + "gpio95", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const sdc41_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const sdc40_groups[] = { + "gpio96", +}; +static const char * const phase_flag3_groups[] = { + "gpio96", +}; +static const char * const mdp_vsync_b_groups[] = { + "gpio97", "gpio98", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const blsp_uart8_groups[] = { + "gpio100", "gpio101", +}; +static const char * const blsp11_i2c_groups[] = { + "gpio102", "gpio103", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const phase_flag5_groups[] = { + "gpio103", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const phase_flag16_groups[] = { + "gpio114", +}; +static const char * const nav_dr_groups[] = { + "gpio115", +}; +static const char * const phase_flag11_groups[] = { + "gpio115", +}; +static const char * const phase_flag12_groups[] = { + "gpio116", +}; +static const char * const phase_flag13_groups[] = { + "gpio117", +}; +static const char * const atest_char_groups[] = { + "gpio117", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const phase_flag17_groups[] = { + "gpio118", +}; +static const char * const atest_char3_groups[] = { + "gpio118", +}; +static const char * const phase_flag18_groups[] = { + "gpio119", +}; +static const char * const atest_char2_groups[] = { + "gpio119", +}; +static const char * const phase_flag19_groups[] = { + "gpio120", +}; +static const char * const atest_char1_groups[] = { + "gpio120", +}; +static const char * const phase_flag20_groups[] = { + "gpio121", +}; +static const char * const atest_char0_groups[] = { + "gpio121", +}; +static const char * const phase_flag21_groups[] = { + "gpio122", +}; +static const char * const phase_flag22_groups[] = { + "gpio123", +}; +static const char * const phase_flag23_groups[] = { + "gpio124", +}; +static const char * const phase_flag24_groups[] = { + "gpio125", +}; +static const char * const phase_flag25_groups[] = { + "gpio126", +}; +static const char * const modem_tsync_groups[] = { + "gpio128", +}; +static const char * const nav_pps_groups[] = { + "gpio128", +}; +static const char * const phase_flag26_groups[] = { + "gpio128", +}; +static const char * const phase_flag27_groups[] = { + "gpio129", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const phase_flag28_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const phase_flag6_groups[] = { + "gpio131", +}; +static const char * const phase_flag29_groups[] = { + "gpio132", +}; +static const char * const phase_flag30_groups[] = { + "gpio133", +}; +static const char * const phase_flag31_groups[] = { + "gpio134", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const ssbi1_groups[] = { + "gpio142", +}; +static const char * const isense_dbg_groups[] = { + "gpio143", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; + +static const struct msm_function msmhamster_functions[] = { + FUNCTION(blsp_spi1), + FUNCTION(gpio), + FUNCTION(blsp_uim1_a), + FUNCTION(blsp_uart1_a), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_spi8), + FUNCTION(blsp_uart8_a), + FUNCTION(blsp_uim8_a), + FUNCTION(qdss_cti0_b), + FUNCTION(blsp_i2c8), + FUNCTION(ddr_bist), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(blsp_spi4), + FUNCTION(blsp_uart1_b), + FUNCTION(blsp_uim1_b), + FUNCTION(wlan1_adc1), + FUNCTION(atest_usb13), + FUNCTION(bimc_dte1), + FUNCTION(tsif1_sync), + FUNCTION(wlan1_adc0), + FUNCTION(atest_usb12), + FUNCTION(bimc_dte0), + FUNCTION(mdp_vsync_a), + FUNCTION(blsp_i2c4), + FUNCTION(atest_gpsadc1), + FUNCTION(wlan2_adc1), + FUNCTION(atest_usb11), + FUNCTION(edp_lcd), + FUNCTION(dbg_out), + FUNCTION(atest_gpsadc0), + FUNCTION(wlan2_adc0), + FUNCTION(atest_usb10), + FUNCTION(mdp_vsync), + FUNCTION(m_voc), + FUNCTION(cam_mclk), + FUNCTION(pll_bypassnl), + FUNCTION(qdss_gpio0), + FUNCTION(pll_reset), + FUNCTION(qdss_gpio1), + FUNCTION(qdss_gpio2), + FUNCTION(qdss_gpio3), + FUNCTION(cci_i2c), + FUNCTION(qdss_gpio4), + FUNCTION(phase_flag14), + FUNCTION(qdss_gpio5), + FUNCTION(phase_flag15), + FUNCTION(qdss_gpio6), + FUNCTION(qdss_gpio7), + FUNCTION(cci_timer4), + FUNCTION(blsp2_spi), + FUNCTION(qdss_gpio11), + FUNCTION(qdss_gpio12), + FUNCTION(qdss_gpio13), + FUNCTION(qdss_gpio14), + FUNCTION(qdss_gpio15), + FUNCTION(cci_timer0), + FUNCTION(qdss_gpio8), + FUNCTION(vsense_data0), + FUNCTION(cci_timer1), + FUNCTION(qdss_gpio), + FUNCTION(vsense_data1), + FUNCTION(cci_timer2), + FUNCTION(blsp1_spi_b), + FUNCTION(qdss_gpio9), + FUNCTION(vsense_mode), + FUNCTION(cci_timer3), + FUNCTION(cci_async), + FUNCTION(blsp1_spi_a), + FUNCTION(qdss_gpio10), + FUNCTION(vsense_clkout), + FUNCTION(hdmi_rcv), + FUNCTION(hdmi_cec), + FUNCTION(blsp_spi2), + FUNCTION(blsp_uart2_a), + FUNCTION(blsp_uim2_a), + FUNCTION(pwr_modem), + FUNCTION(hdmi_ddc), + FUNCTION(blsp_i2c2), + FUNCTION(pwr_nav), + FUNCTION(pwr_crypto), + FUNCTION(hdmi_hot), + FUNCTION(edp_hot), + FUNCTION(pci_e0), + FUNCTION(jitter_bist), + FUNCTION(agera_pll), + FUNCTION(atest_tsens), + FUNCTION(usb_phy), + FUNCTION(lpass_slimbus), + FUNCTION(sd_write), + FUNCTION(tsif1_error), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart3_b), + FUNCTION(blsp_uim3_b), + FUNCTION(blsp_i2c6), + FUNCTION(bt_reset), + FUNCTION(blsp_spi3), + FUNCTION(blsp_uart3_a), + FUNCTION(blsp_uim3_a), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_spi9), + FUNCTION(blsp_uart9_a), + FUNCTION(blsp_uim9_a), + FUNCTION(blsp10_spi_b), + FUNCTION(qdss_cti0_a), + FUNCTION(blsp_i2c9), + FUNCTION(blsp10_spi_a), + FUNCTION(blsp_spi7), + FUNCTION(blsp_uart7_a), + FUNCTION(blsp_uim7_a), + FUNCTION(blsp_i2c7), + FUNCTION(qua_mi2s), + FUNCTION(blsp10_spi), + FUNCTION(gcc_gp1_a), + FUNCTION(ssc_irq), + FUNCTION(blsp_spi11), + FUNCTION(blsp_uart8_b), + FUNCTION(blsp_uim8_b), + FUNCTION(gcc_gp2_a), + FUNCTION(qdss_cti1_a), + FUNCTION(gcc_gp3_a), + FUNCTION(blsp_i2c11), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(cri_trng), + FUNCTION(pri_mi2s), + FUNCTION(sp_cmu), + FUNCTION(blsp_spi10), + FUNCTION(blsp_uart7_b), + FUNCTION(blsp_uim7_b), + FUNCTION(pri_mi2s_ws), + FUNCTION(blsp_i2c10), + FUNCTION(spkr_i2s), + FUNCTION(audio_ref), + FUNCTION(blsp9_spi), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(btfm_slimbus), + FUNCTION(phase_flag0), + FUNCTION(ter_mi2s), + FUNCTION(phase_flag7), + FUNCTION(phase_flag8), + FUNCTION(phase_flag9), + FUNCTION(phase_flag4), + FUNCTION(gcc_gp1_b), + FUNCTION(sec_mi2s), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart9_b), + FUNCTION(blsp_uim9_b), + FUNCTION(gcc_gp2_b), + FUNCTION(gcc_gp3_b), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uart2_b), + FUNCTION(blsp_uim2_b), + FUNCTION(blsp_i2c5), + FUNCTION(tsif1_clk), + FUNCTION(phase_flag10), + FUNCTION(tsif1_en), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(blsp1_spi), + FUNCTION(tgu_ch0), + FUNCTION(qdss_cti1_b), + FUNCTION(tsif1_data), + FUNCTION(sdc4_cmd), + FUNCTION(tgu_ch1), + FUNCTION(phase_flag1), + FUNCTION(tsif2_error), + FUNCTION(sdc43), + FUNCTION(vfr_1), + FUNCTION(phase_flag2), + FUNCTION(tsif2_clk), + FUNCTION(sdc4_clk), + FUNCTION(tsif2_en), + FUNCTION(sdc42), + FUNCTION(sd_card), + FUNCTION(tsif2_data), + FUNCTION(sdc41), + FUNCTION(tsif2_sync), + FUNCTION(sdc40), + FUNCTION(phase_flag3), + FUNCTION(mdp_vsync_b), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(blsp_uart8), + FUNCTION(blsp11_i2c), + FUNCTION(prng_rosc), + FUNCTION(phase_flag5), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(uim2_present), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(uim_batt), + FUNCTION(phase_flag16), + FUNCTION(nav_dr), + FUNCTION(phase_flag11), + FUNCTION(phase_flag12), + FUNCTION(phase_flag13), + FUNCTION(atest_char), + FUNCTION(adsp_ext), + FUNCTION(phase_flag17), + FUNCTION(atest_char3), + FUNCTION(phase_flag18), + FUNCTION(atest_char2), + FUNCTION(phase_flag19), + FUNCTION(atest_char1), + FUNCTION(phase_flag20), + FUNCTION(atest_char0), + FUNCTION(phase_flag21), + FUNCTION(phase_flag22), + FUNCTION(phase_flag23), + FUNCTION(phase_flag24), + FUNCTION(phase_flag25), + FUNCTION(modem_tsync), + FUNCTION(nav_pps), + FUNCTION(phase_flag26), + FUNCTION(phase_flag27), + FUNCTION(qlink_request), + FUNCTION(phase_flag28), + FUNCTION(qlink_enable), + FUNCTION(phase_flag6), + FUNCTION(phase_flag29), + FUNCTION(phase_flag30), + FUNCTION(phase_flag31), + FUNCTION(pa_indicator), + FUNCTION(ssbi1), + FUNCTION(isense_dbg), + FUNCTION(mss_lte), +}; + +static const struct msm_pingroup msmhamster_groups[] = { + PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA, + NA, NA), + PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA, + qdss_cti0_b, NA, NA, NA, NA), + PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA, + qdss_cti0_b, NA, NA, NA, NA), + PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, NA, NA, NA, NA, + NA, NA), + PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, NA, + atest_tsens2, atest_usb1, NA, NA), + PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, NA, ddr_bist, + NA, wlan1_adc1, atest_usb13, bimc_dte1), + PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, + ddr_bist, NA, wlan1_adc0, atest_usb12, bimc_dte0), + PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, + ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1), + PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, + blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10), + PINGROUP(12, EAST, mdp_vsync, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss_gpio0, NA, NA, NA, NA, + NA, NA), + PINGROUP(14, EAST, cam_mclk, pll_reset, qdss_gpio1, NA, NA, NA, NA, + NA, NA), + PINGROUP(15, EAST, cam_mclk, qdss_gpio2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, EAST, cam_mclk, qdss_gpio3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, EAST, cci_i2c, qdss_gpio4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, EAST, cci_i2c, phase_flag14, qdss_gpio5, NA, NA, NA, NA, + NA, NA), + PINGROUP(19, EAST, cci_i2c, phase_flag15, qdss_gpio6, NA, NA, NA, NA, + NA, NA), + PINGROUP(20, EAST, cci_i2c, qdss_gpio7, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, EAST, cci_timer0, NA, qdss_gpio8, vsense_data0, NA, NA, + NA, NA, NA), + PINGROUP(22, EAST, cci_timer1, NA, qdss_gpio, vsense_data1, NA, NA, NA, + NA, NA), + PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss_gpio9, vsense_mode, + NA, NA, NA, NA, NA), + PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, NA, qdss_gpio10, + vsense_clkout, NA, NA, NA), + PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, NA, qdss_gpio11, + NA, NA, NA, NA), + PINGROUP(26, EAST, cci_async, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, EAST, blsp1_spi_a, qdss_gpio13, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(28, EAST, blsp1_spi_b, qdss_gpio14, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(29, EAST, blsp2_spi, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA), + PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss_gpio, NA, NA, NA, NA, NA, + NA), + PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, + pwr_modem, NA, NA, NA, NA), + PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, + pwr_nav, NA, NA, NA, NA), + PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, + pwr_crypto, NA, NA, NA, NA), + PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, + blsp_uim2_a, NA, NA, NA, NA), + PINGROUP(35, WEST, pci_e0, jitter_bist, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, WEST, pci_e0, agera_pll, NA, atest_tsens, NA, NA, NA, NA, + NA), + PINGROUP(37, WEST, agera_pll, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, WEST, usb_phy, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, WEST, lpass_slimbus, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, EAST, sd_write, tsif1_error, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA, + qdss_gpio6, NA, NA, NA, NA), + PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA, + qdss_gpio7, NA, NA, NA, NA), + PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio14, + NA, NA, NA, NA), + PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio15, + NA, NA, NA, NA), + PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA, + NA, NA), + PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA, + NA, NA), + PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, + qdss_cti0_a, NA, NA, NA, NA), + PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, + qdss_cti0_a, NA, NA, NA, NA), + PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, + NA, NA, NA, NA, NA), + PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, + NA, NA, NA, NA, NA), + PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA, + NA, NA), + PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA, + NA, NA), + PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(58, NORTH, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, + gcc_gp2_a, NA, qdss_cti1_a, NA, NA), + PINGROUP(59, NORTH, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, + gcc_gp3_a, NA, qdss_cti1_a, NA, NA), + PINGROUP(60, NORTH, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, + cri_trng0, NA, NA, NA, NA), + PINGROUP(61, NORTH, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, + cri_trng1, NA, NA, NA, NA), + PINGROUP(62, WEST, qua_mi2s, cri_trng, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, WEST, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, WEST, pri_mi2s, sp_cmu, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, NA, + NA, NA, NA, NA), + PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, + NA, NA, NA, NA, NA), + PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA, + NA, NA, NA, NA), + PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA, + NA, NA, NA, NA), + PINGROUP(69, WEST, spkr_i2s, audio_ref, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA, + NA, NA), + PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, + tsense_pwm2, NA, NA, NA, NA), + PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA, + NA, NA), + PINGROUP(73, WEST, btfm_slimbus, phase_flag0, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag7, NA, NA, NA, NA, + NA, NA), + PINGROUP(75, WEST, ter_mi2s, phase_flag8, qdss_gpio8, NA, NA, NA, NA, + NA, NA), + PINGROUP(76, WEST, ter_mi2s, phase_flag9, qdss_gpio9, NA, NA, NA, NA, + NA, NA), + PINGROUP(77, WEST, ter_mi2s, phase_flag4, qdss_gpio10, NA, NA, NA, NA, + NA, NA), + PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, WEST, sec_mi2s, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA), + PINGROUP(80, WEST, sec_mi2s, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA), + PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, + gcc_gp2_b, NA, NA, NA, NA), + PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, + gcc_gp3_b, NA, NA, NA, NA), + PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA, + NA, NA, NA, NA), + PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA, NA, NA, + NA, NA, NA), + PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA, + NA, NA, NA), + PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA, + NA, NA, NA), + PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(89, EAST, tsif1_clk, phase_flag10, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, NA), + PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag1, + qdss_cti1_b, NA, NA, NA, NA), + PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag2, NA, NA, NA, + NA, NA), + PINGROUP(93, EAST, tsif2_clk, sdc4_clk, NA, qdss_gpio13, NA, NA, NA, + NA, NA), + PINGROUP(94, EAST, tsif2_en, sdc42, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, EAST, tsif2_data, sdc41, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag3, NA, NA, NA, NA, NA, + NA), + PINGROUP(97, WEST, NA, mdp_vsync_b, ldo_en, NA, NA, NA, NA, NA, NA), + PINGROUP(98, WEST, NA, mdp_vsync_b, ldo_update, NA, NA, NA, NA, NA, + NA), + PINGROUP(99, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, WEST, NA, NA, blsp_uart8, NA, NA, NA, NA, NA, NA), + PINGROUP(101, WEST, NA, blsp_uart8, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, WEST, NA, blsp11_i2c, prng_rosc, NA, NA, NA, NA, NA, + NA), + PINGROUP(103, WEST, NA, blsp11_i2c, phase_flag5, NA, NA, NA, NA, NA, + NA), + PINGROUP(104, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NORTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NORTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NORTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NORTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NORTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NORTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NORTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NORTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NORTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, WEST, NA, NA, phase_flag16, NA, NA, NA, NA, NA, NA), + PINGROUP(115, WEST, NA, nav_dr, phase_flag11, NA, NA, NA, NA, NA, NA), + PINGROUP(116, WEST, phase_flag12, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, EAST, phase_flag13, qdss_gpio0, atest_char, NA, NA, NA, + NA, NA, NA), + PINGROUP(118, EAST, adsp_ext, phase_flag17, qdss_gpio1, atest_char3, + NA, NA, NA, NA, NA), + PINGROUP(119, EAST, phase_flag18, qdss_gpio2, atest_char2, NA, NA, NA, + NA, NA, NA), + PINGROUP(120, EAST, phase_flag19, qdss_gpio3, atest_char1, NA, NA, NA, + NA, NA, NA), + PINGROUP(121, EAST, phase_flag20, qdss_gpio4, atest_char0, NA, NA, NA, + NA, NA, NA), + PINGROUP(122, EAST, phase_flag21, qdss_gpio5, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(123, EAST, phase_flag22, qdss_gpio, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(124, EAST, phase_flag23, qdss_gpio, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(125, EAST, phase_flag24, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, EAST, phase_flag25, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag26, NA, NA, NA, + NA, NA, NA), + PINGROUP(129, WEST, phase_flag27, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NORTH, qlink_request, phase_flag28, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(131, NORTH, qlink_enable, phase_flag6, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(132, WEST, NA, phase_flag29, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, WEST, phase_flag30, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, WEST, phase_flag31, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, WEST, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, WEST, NA, ssbi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, WEST, isense_dbg, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data msmhamster_pinctrl = { + .pins = msmhamster_pins, + .npins = ARRAY_SIZE(msmhamster_pins), + .functions = msmhamster_functions, + .nfunctions = ARRAY_SIZE(msmhamster_functions), + .groups = msmhamster_groups, + .ngroups = ARRAY_SIZE(msmhamster_groups), + .ngpios = 153, +}; + +static int msmhamster_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msmhamster_pinctrl); +} + +static const struct of_device_id msmhamster_pinctrl_of_match[] = { + { .compatible = "qcom,msmhamster-pinctrl", }, + { }, +}; + +static struct platform_driver msmhamster_pinctrl_driver = { + .driver = { + .name = "msmhamster-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msmhamster_pinctrl_of_match, + }, + .probe = msmhamster_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msmhamster_pinctrl_init(void) +{ + return platform_driver_register(&msmhamster_pinctrl_driver); +} +arch_initcall(msmhamster_pinctrl_init); + +static void __exit msmhamster_pinctrl_exit(void) +{ + platform_driver_unregister(&msmhamster_pinctrl_driver); +} +module_exit(msmhamster_pinctrl_exit); + +MODULE_DESCRIPTION("QTI msmhamster pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msmhamster_pinctrl_of_match); diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 774ab65fe212..1ae5426aa38e 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -521,6 +521,9 @@ static struct msm_soc_info cpu_of_id[] = { /* Cobalt ID */ [292] = {MSM_CPU_COBALT, "MSMCOBALT"}, + /* Cobalt ID */ + [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, + /* Uninitialized IDs are not known to run Linux. MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are considered as unknown CPU. */ @@ -1118,6 +1121,10 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 292; strlcpy(dummy_socinfo.build_id, "msmcobalt - ", sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_msmhamster()) { + dummy_socinfo.id = 306; + strlcpy(dummy_socinfo.build_id, "msmhamster - ", + sizeof(dummy_socinfo.build_id)); } strlcat(dummy_socinfo.build_id, "Dummy socinfo", diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 4fa506963ca1..03f71bf574e0 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -35,6 +35,7 @@ #include <linux/of.h> #include <linux/acpi.h> #include <linux/pinctrl/consumer.h> +#include <linux/irq.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -991,7 +992,7 @@ static int dwc3_probe(struct platform_device *pdev) u8 hird_threshold; u32 fladj = 0; u32 num_evt_buffs; - + int irq; int ret; void __iomem *regs; @@ -1016,6 +1017,20 @@ static int dwc3_probe(struct platform_device *pdev) dwc->xhci_resources[1].flags = res->flags; dwc->xhci_resources[1].name = res->name; + irq = platform_get_irq(to_platform_device(dwc->dev), 0); + + /* will be enabled in dwc3_msm_resume() */ + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret = devm_request_irq(dev, irq, dwc3_interrupt, IRQF_SHARED, "dwc3", + dwc); + if (ret) { + dev_err(dwc->dev, "failed to request irq #%d --> %d\n", + irq, ret); + return -ENODEV; + } + + dwc->irq = irq; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "missing memory resource\n"); diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index c053949ff6cd..5dbe537a41ea 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -3140,13 +3140,6 @@ static void dwc3_otg_sm_work(struct work_struct *w) break; dbg_event(0xFF, "Exit UNDEF", 0); - - /* - * The first call to msm_resume will enable this IRQ which - * needs to first be disabled else it will be unbalanced. - */ - if (dwc->irq) - disable_irq(dwc->irq); mdwc->otg_state = OTG_STATE_B_IDLE; /* fall-through */ case OTG_STATE_B_IDLE: diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index dc10f299b2a6..98df702b291d 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1905,7 +1905,6 @@ void dwc3_gadget_disable_irq(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); } -static irqreturn_t dwc3_interrupt(int irq, void *_dwc); static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc); @@ -2055,16 +2054,6 @@ static int dwc3_gadget_start(struct usb_gadget *g, struct dwc3 *dwc = gadget_to_dwc(g); unsigned long flags; int ret = 0; - int irq; - - irq = platform_get_irq(to_platform_device(dwc->dev), 0); - dwc->irq = irq; - ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, "dwc3", dwc); - if (ret) { - dev_err(dwc->dev, "failed to request irq #%d --> %d\n", - irq, ret); - goto err0; - } spin_lock_irqsave(&dwc->lock, flags); @@ -2073,7 +2062,7 @@ static int dwc3_gadget_start(struct usb_gadget *g, dwc->gadget.name, dwc->gadget_driver->driver.name); ret = -EBUSY; - goto err1; + goto err0; } dwc->gadget_driver = driver; @@ -2087,11 +2076,8 @@ static int dwc3_gadget_start(struct usb_gadget *g, spin_unlock_irqrestore(&dwc->lock, flags); return 0; -err1: - spin_unlock_irqrestore(&dwc->lock, flags); - free_irq(irq, dwc); - err0: + spin_unlock_irqrestore(&dwc->lock, flags); return ret; } @@ -2099,7 +2085,6 @@ static int dwc3_gadget_stop(struct usb_gadget *g) { struct dwc3 *dwc = gadget_to_dwc(g); unsigned long flags; - int irq; pm_runtime_get_sync(dwc->dev); dbg_event(0xFF, "Stop gsync", @@ -2121,9 +2106,6 @@ static int dwc3_gadget_stop(struct usb_gadget *g) pm_runtime_put_autosuspend(dwc->dev); dbg_event(0xFF, "Auto_susgsync", 0); - irq = platform_get_irq(to_platform_device(dwc->dev), 0); - free_irq(irq, dwc); - return 0; } @@ -3417,7 +3399,7 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) return IRQ_WAKE_THREAD; } -static irqreturn_t dwc3_interrupt(int irq, void *_dwc) +irqreturn_t dwc3_interrupt(int irq, void *_dwc) { struct dwc3 *dwc = _dwc; int i; diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index 719326d14e6c..3abd6379164e 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -96,6 +96,7 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, gfp_t gfp_flags); int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol); void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); +irqreturn_t dwc3_interrupt(int irq, void *_dwc); static inline dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, struct dwc3_trb *trb) diff --git a/drivers/video/fbdev/msm/mdss_dba_utils.c b/drivers/video/fbdev/msm/mdss_dba_utils.c index b14a83e863ab..fa78bd0166ea 100644 --- a/drivers/video/fbdev/msm/mdss_dba_utils.c +++ b/drivers/video/fbdev/msm/mdss_dba_utils.c @@ -300,7 +300,7 @@ static void mdss_dba_utils_dba_cb(void *data, enum msm_dba_callback_event event) bool operands_present = false; u32 no_of_operands, size, i; u32 operands_offset = MAX_CEC_FRAME_SIZE - MAX_OPERAND_SIZE; - struct msm_hdmi_audio_edid_blk blk; + struct msm_ext_disp_audio_edid_blk blk; if (!udata) { pr_err("Invalid data\n"); diff --git a/drivers/video/fbdev/msm/mdss_hdmi_audio.c b/drivers/video/fbdev/msm/mdss_hdmi_audio.c index d949a86a8f5d..780629eb25b9 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_audio.c +++ b/drivers/video/fbdev/msm/mdss_hdmi_audio.c @@ -64,7 +64,7 @@ enum hdmi_audio_sample_rates { struct hdmi_audio { struct dss_io_data *io; - struct msm_hdmi_audio_setup_params params; + struct msm_ext_disp_audio_setup_params params; struct switch_dev sdev; u32 pclk; bool ack_enabled; @@ -145,7 +145,7 @@ static void hdmi_audio_acr_enable(struct hdmi_audio *audio) { struct dss_io_data *io; struct hdmi_audio_acr acr; - struct msm_hdmi_audio_setup_params *params; + struct msm_ext_disp_audio_setup_params *params; u32 pclk, layout, multiplier, sample_rate; u32 acr_pkt_ctl, aud_pkt_ctl2, acr_reg_cts, acr_reg_n; @@ -327,7 +327,7 @@ end: } static int hdmi_audio_on(void *ctx, u32 pclk, - struct msm_hdmi_audio_setup_params *params) + struct msm_ext_disp_audio_setup_params *params) { struct hdmi_audio *audio = ctx; int rc = 0; diff --git a/drivers/video/fbdev/msm/mdss_hdmi_audio.h b/drivers/video/fbdev/msm/mdss_hdmi_audio.h index c53bfd9b1ff2..57670a84988c 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_audio.h +++ b/drivers/video/fbdev/msm/mdss_hdmi_audio.h @@ -14,7 +14,7 @@ #define __MDSS_HDMI_AUDIO_H__ #include <linux/mdss_io_util.h> -#include <linux/msm_hdmi.h> +#include <linux/msm_ext_display.h> #define AUDIO_ACK_SET_ENABLE BIT(5) #define AUDIO_ACK_ENABLE BIT(4) @@ -46,7 +46,7 @@ struct hdmi_audio_status { */ struct hdmi_audio_ops { int (*on)(void *ctx, u32 pclk, - struct msm_hdmi_audio_setup_params *params); + struct msm_ext_disp_audio_setup_params *params); void (*off)(void *ctx); void (*reset)(void *ctx); void (*status)(void *ctx, struct hdmi_audio_status *status); diff --git a/drivers/video/fbdev/msm/mdss_hdmi_edid.c b/drivers/video/fbdev/msm/mdss_hdmi_edid.c index f5c45571f0d2..018d7519bf8f 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_edid.c +++ b/drivers/video/fbdev/msm/mdss_hdmi_edid.c @@ -2365,7 +2365,8 @@ bool hdmi_edid_get_sink_scrambler_support(void *input) return scramble_support; } -int hdmi_edid_get_audio_blk(void *input, struct msm_hdmi_audio_edid_blk *blk) +int hdmi_edid_get_audio_blk(void *input, + struct msm_ext_disp_audio_edid_blk *blk) { struct hdmi_edid_ctrl *edid_ctrl = (struct hdmi_edid_ctrl *)input; diff --git a/drivers/video/fbdev/msm/mdss_hdmi_edid.h b/drivers/video/fbdev/msm/mdss_hdmi_edid.h index d485e370d3aa..6cf0f1240f8a 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_edid.h +++ b/drivers/video/fbdev/msm/mdss_hdmi_edid.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,7 +13,7 @@ #ifndef __HDMI_EDID_H__ #define __HDMI_EDID_H__ -#include <linux/msm_hdmi.h> +#include <linux/msm_ext_display.h> #include "mdss_hdmi_util.h" #define EDID_BLOCK_SIZE 0x80 @@ -35,7 +35,7 @@ u32 hdmi_edid_get_sink_mode(void *edid_ctrl); bool hdmi_edid_get_sink_scrambler_support(void *input); bool hdmi_edid_get_scdc_support(void *input); int hdmi_edid_get_audio_blk(void *edid_ctrl, - struct msm_hdmi_audio_edid_blk *blk); + struct msm_ext_disp_audio_edid_blk *blk); void hdmi_edid_set_video_resolution(void *edid_ctrl, u32 resolution, bool reset); void hdmi_edid_deinit(void *edid_ctrl); diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.c b/drivers/video/fbdev/msm/mdss_hdmi_tx.c index b300c4aba599..94b7bf02ccd0 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_tx.c +++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.c @@ -245,7 +245,7 @@ fail: return rc; } -int register_hdmi_cable_notification(struct hdmi_cable_notify *handler) +int register_hdmi_cable_notification(struct ext_disp_cable_notify *handler) { struct hdmi_tx_ctrl *hdmi_ctrl = NULL; struct list_head *pos; @@ -271,7 +271,7 @@ int register_hdmi_cable_notification(struct hdmi_cable_notify *handler) return handler->status; } /* register_hdmi_cable_notification */ -int unregister_hdmi_cable_notification(struct hdmi_cable_notify *handler) +int unregister_hdmi_cable_notification(struct ext_disp_cable_notify *handler) { struct hdmi_tx_ctrl *hdmi_ctrl = NULL; @@ -297,7 +297,7 @@ int unregister_hdmi_cable_notification(struct hdmi_cable_notify *handler) static void hdmi_tx_cable_notify_work(struct work_struct *work) { struct hdmi_tx_ctrl *hdmi_ctrl = NULL; - struct hdmi_cable_notify *pos; + struct ext_disp_cable_notify *pos; hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, cable_notify_work); @@ -3060,7 +3060,7 @@ static void hdmi_tx_phy_reset(struct hdmi_tx_ctrl *hdmi_ctrl) } /* hdmi_tx_phy_reset */ static int hdmi_tx_audio_info_setup(struct platform_device *pdev, - struct msm_hdmi_audio_setup_params *params) + struct msm_ext_disp_audio_setup_params *params) { int rc = 0; struct hdmi_tx_ctrl *hdmi_ctrl = platform_get_drvdata(pdev); @@ -3077,7 +3077,7 @@ static int hdmi_tx_audio_info_setup(struct platform_device *pdev, if (!is_mode_dvi && hdmi_tx_is_panel_on(hdmi_ctrl)) { memcpy(&hdmi_ctrl->audio_params, params, - sizeof(struct msm_hdmi_audio_setup_params)); + sizeof(struct msm_ext_disp_audio_setup_params)); hdmi_tx_audio_setup(hdmi_ctrl); } else { @@ -3103,7 +3103,7 @@ static int hdmi_tx_audio_info_setup(struct platform_device *pdev, } static int hdmi_tx_get_audio_edid_blk(struct platform_device *pdev, - struct msm_hdmi_audio_edid_blk *blk) + struct msm_ext_disp_audio_edid_blk *blk) { struct hdmi_tx_ctrl *hdmi_ctrl = platform_get_drvdata(pdev); @@ -3217,7 +3217,7 @@ static int hdmi_tx_get_cable_status(struct platform_device *pdev, u32 vote) } int msm_hdmi_register_audio_codec(struct platform_device *pdev, - struct msm_hdmi_audio_codec_ops *ops) + struct msm_ext_disp_audio_codec_ops *ops) { struct hdmi_tx_ctrl *hdmi_ctrl = platform_get_drvdata(pdev); @@ -3228,7 +3228,7 @@ int msm_hdmi_register_audio_codec(struct platform_device *pdev, ops->audio_info_setup = hdmi_tx_audio_info_setup; ops->get_audio_edid_blk = hdmi_tx_get_audio_edid_blk; - ops->hdmi_cable_status = hdmi_tx_get_cable_status; + ops->cable_status = hdmi_tx_get_cable_status; return 0; } /* hdmi_tx_audio_register */ @@ -3473,7 +3473,7 @@ static inline void hdmi_tx_audio_off(struct hdmi_tx_ctrl *hdmi_ctrl) hdmi_ctrl->audio_ops.off(hdmi_ctrl->audio_data); memset(&hdmi_ctrl->audio_params, 0, - sizeof(struct msm_hdmi_audio_setup_params)); + sizeof(struct msm_ext_disp_audio_setup_params)); } static int hdmi_tx_power_off(struct mdss_panel_data *panel_data) diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.h b/drivers/video/fbdev/msm/mdss_hdmi_tx.h index 170837dcc9e6..a33ed2d4a3d1 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_tx.h +++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.h @@ -194,7 +194,7 @@ struct hdmi_tx_ctrl { struct cec_ops hdmi_cec_ops; struct cec_cbs hdmi_cec_cbs; struct hdmi_audio_ops audio_ops; - struct msm_hdmi_audio_setup_params audio_params; + struct msm_ext_disp_audio_setup_params audio_params; char disp_switch_name[MAX_SWITCH_NAME_SIZE]; bool power_data_enable[HDMI_TX_MAX_PM]; diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index a63822e56429..829599aaf4de 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -230,6 +230,7 @@ #define clk_gcc_ufs_ice_core_clk 0x310b0710 #define clk_gcc_ufs_phy_aux_clk 0x17acc8fb #define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde #define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a #define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 #define clk_ufs_rx_symbol_0_clk 0x17a0f1cd diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h index befb603e89d8..2c92246827b6 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h @@ -198,6 +198,7 @@ #define GCC_UFS_AHB_CBCR 0x7500C #define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 #define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C #define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 #define GCC_UFS_ICE_CORE_CBCR 0x7600C #define GCC_UFS_PHY_AUX_CBCR 0x76040 diff --git a/include/linux/msm_hdmi.h b/include/linux/msm_ext_display.h index 45b206b86765..eb90b49477cc 100644 --- a/include/linux/msm_hdmi.h +++ b/include/linux/msm_ext_display.h @@ -1,6 +1,6 @@ -/* include/linux/msm_hdmi.h +/* include/linux/msm_ext_display.h * - * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2016 The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -11,32 +11,32 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef _MSM_HDMI_H_ -#define _MSM_HDMI_H_ +#ifndef _MSM_EXT_DISPLAY_H_ +#define _MSM_EXT_DISPLAY_H_ #include <linux/device.h> #include <linux/platform_device.h> /* - * HDMI cable notify handler sturcture. + * External display cable notify handler structure. * link A link for the linked list - * status Current status of HDMI cable connection + * status Current status of HDMI/DP cable connection * hpd_notify Callback function to provide cable status */ -struct hdmi_cable_notify { +struct ext_disp_cable_notify { struct list_head link; int status; - void (*hpd_notify) (struct hdmi_cable_notify *h); + void (*hpd_notify)(struct ext_disp_cable_notify *h); }; -struct msm_hdmi_audio_edid_blk { +struct msm_ext_disp_audio_edid_blk { u8 *audio_data_blk; unsigned int audio_data_blk_size; /* in bytes */ u8 *spk_alloc_data_blk; unsigned int spk_alloc_data_blk_size; /* in bytes */ }; -struct msm_hdmi_audio_setup_params { +struct msm_ext_disp_audio_setup_params { u32 sample_rate_hz; u32 num_of_channels; u32 channel_allocation; @@ -45,14 +45,24 @@ struct msm_hdmi_audio_setup_params { u32 sample_present; }; -struct msm_hdmi_audio_codec_ops { +struct msm_ext_disp_audio_codec_ops { int (*audio_info_setup)(struct platform_device *pdev, - struct msm_hdmi_audio_setup_params *params); - int (*get_audio_edid_blk) (struct platform_device *pdev, - struct msm_hdmi_audio_edid_blk *blk); - int (*hdmi_cable_status) (struct platform_device *pdev, u32 vote); + struct msm_ext_disp_audio_setup_params *params); + int (*get_audio_edid_blk)(struct platform_device *pdev, + struct msm_ext_disp_audio_edid_blk *blk); + int (*cable_status)(struct platform_device *pdev, u32 vote); }; +#ifdef CONFIG_FB_MSM_MDSS_DP_PANEL +int msm_dp_register_audio_codec(struct platform_device *pdev, + struct msm_ext_disp_audio_codec_ops *ops); + +#else +static inline int msm_dp_register_audio_codec(struct platform_device *pdev, + struct msm_ext_disp_audio_codec_ops *ops) { + return 0; +} +#endif /* CONFIG_FB_MSM_MDSS_DP_PANEL */ #ifdef CONFIG_FB_MSM_MDSS_HDMI_PANEL /* * Register for HDMI cable connect or disconnect notification. @@ -60,7 +70,7 @@ struct msm_hdmi_audio_codec_ops { * @return negative value as error otherwise current status of cable */ int register_hdmi_cable_notification( - struct hdmi_cable_notify *handler); + struct ext_disp_cable_notify *handler); /* * Un-register for HDMI cable connect or disconnect notification. @@ -68,26 +78,26 @@ int register_hdmi_cable_notification( * @return negative value as error */ int unregister_hdmi_cable_notification( - struct hdmi_cable_notify *handler); + struct ext_disp_cable_notify *handler); int msm_hdmi_register_audio_codec(struct platform_device *pdev, - struct msm_hdmi_audio_codec_ops *ops); + struct msm_ext_disp_audio_codec_ops *ops); #else static inline int register_hdmi_cable_notification( - struct hdmi_cable_notify *handler) { + struct ext_disp_cable_notify *handler) { return 0; } static inline int unregister_hdmi_cable_notification( - struct hdmi_cable_notify *handler) { + struct ext_disp_cable_notify *handler) { return 0; } static inline int msm_hdmi_register_audio_codec(struct platform_device *pdev, - struct msm_hdmi_audio_codec_ops *ops) { + struct msm_ext_disp_audio_codec_ops *ops) { return 0; } #endif /* CONFIG_FB_MSM_MDSS_HDMI_PANEL */ -#endif /*_MSM_HDMI_H_*/ +#endif /*_MSM_EXT_DISPLAY_H_*/ diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index a836481a37c9..a39e42ce4593 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -90,6 +90,8 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8929") #define early_machine_is_msmcobalt() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmcobalt") +#define early_machine_is_msmhamster() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster") #else #define of_board_is_sim() 0 #define of_board_is_rumi() 0 @@ -124,6 +126,7 @@ #define early_machine_is_msm8976() 0 #define early_machine_is_msm8929() 0 #define early_machine_is_msmcobalt() 0 +#define early_machine_is_msmhamster() 0 #endif #define PLATFORM_SUBTYPE_MDM 1 @@ -181,6 +184,7 @@ enum msm_cpu { MSM_CPU_8976, MSM_CPU_8929, MSM_CPU_COBALT, + MSM_CPU_HAMSTER, }; struct msm_soc_info { diff --git a/mm/Kconfig.debug b/mm/Kconfig.debug index 9ee40661e3cb..9e55d6b141aa 100644 --- a/mm/Kconfig.debug +++ b/mm/Kconfig.debug @@ -16,8 +16,8 @@ config DEBUG_PAGEALLOC select PAGE_POISONING if !ARCH_SUPPORTS_DEBUG_PAGEALLOC ---help--- Unmap pages from the kernel linear mapping after free_pages(). - This results in a large slowdown, but helps to find certain types - of memory corruption. + Depending on runtime enablement, this results in a small or large + slowdown, but helps to find certain types of memory corruption. For architectures which don't enable ARCH_SUPPORTS_DEBUG_PAGEALLOC, fill the pages with poison patterns after free_pages() and verify @@ -26,6 +26,20 @@ config DEBUG_PAGEALLOC that would result in incorrect warnings of memory corruption after a resume because free pages are not saved to the suspend image. + By default this option will have a small overhead, e.g. by not + allowing the kernel mapping to be backed by large pages on some + architectures. Even bigger overhead comes when the debugging is + enabled by DEBUG_PAGEALLOC_ENABLE_DEFAULT or the debug_pagealloc + command line parameter. + +config DEBUG_PAGEALLOC_ENABLE_DEFAULT + bool "Enable debug page memory allocations by default?" + default n + depends on DEBUG_PAGEALLOC + ---help--- + Enable debug page memory allocations by default? This value + can be overridden by debug_pagealloc=off|on. + config PAGE_POISONING bool diff --git a/mm/page_alloc.c b/mm/page_alloc.c index cadce191d555..01b4412d08f0 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -491,7 +491,8 @@ void prep_compound_page(struct page *page, unsigned int order) #ifdef CONFIG_DEBUG_PAGEALLOC unsigned int _debug_guardpage_minorder; -bool _debug_pagealloc_enabled __read_mostly; +bool _debug_pagealloc_enabled __read_mostly + = IS_ENABLED(CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT); bool _debug_guardpage_enabled __read_mostly; static int __init early_debug_pagealloc(char *buf) @@ -502,6 +503,9 @@ static int __init early_debug_pagealloc(char *buf) if (strcmp(buf, "on") == 0) _debug_pagealloc_enabled = true; + if (strcmp(buf, "off") == 0) + _debug_pagealloc_enabled = false; + return 0; } early_param("debug_pagealloc", early_debug_pagealloc); diff --git a/sound/soc/codecs/msm_hdmi_codec_rx.c b/sound/soc/codecs/msm_hdmi_codec_rx.c index 2d08e55eb115..a81d89af51b1 100755 --- a/sound/soc/codecs/msm_hdmi_codec_rx.c +++ b/sound/soc/codecs/msm_hdmi_codec_rx.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -17,7 +17,7 @@ #include <sound/core.h> #include <sound/pcm.h> #include <sound/soc.h> -#include <linux/msm_hdmi.h> +#include <linux/msm_ext_display.h> #define MSM_HDMI_PCM_RATES SNDRV_PCM_RATE_48000 @@ -25,7 +25,7 @@ static int msm_hdmi_audio_codec_return_value; struct msm_hdmi_audio_codec_rx_data { struct platform_device *hdmi_core_pdev; - struct msm_hdmi_audio_codec_ops hdmi_ops; + struct msm_ext_disp_audio_codec_ops hdmi_ops; }; static int msm_hdmi_edid_ctl_info(struct snd_kcontrol *kcontrol, @@ -33,7 +33,7 @@ static int msm_hdmi_edid_ctl_info(struct snd_kcontrol *kcontrol, { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct msm_hdmi_audio_codec_rx_data *codec_data; - struct msm_hdmi_audio_edid_blk edid_blk; + struct msm_ext_disp_audio_edid_blk edid_blk; int rc; codec_data = snd_soc_codec_get_drvdata(codec); @@ -52,7 +52,7 @@ static int msm_hdmi_edid_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct msm_hdmi_audio_codec_rx_data *codec_data; - struct msm_hdmi_audio_edid_blk edid_blk; + struct msm_ext_disp_audio_edid_blk edid_blk; int rc; codec_data = snd_soc_codec_get_drvdata(codec); @@ -91,7 +91,7 @@ static int msm_hdmi_audio_codec_rx_dai_startup( dev_get_drvdata(dai->codec->dev); msm_hdmi_audio_codec_return_value = - codec_data->hdmi_ops.hdmi_cable_status( + codec_data->hdmi_ops.cable_status( codec_data->hdmi_core_pdev, 1); if (IS_ERR_VALUE(msm_hdmi_audio_codec_return_value)) { dev_err(dai->dev, @@ -118,7 +118,7 @@ static int msm_hdmi_audio_codec_rx_dai_hw_params( bool down_mix = 0; u32 num_channels = params_channels(params); int rc = 0; - struct msm_hdmi_audio_setup_params audio_setup_params = {0}; + struct msm_ext_disp_audio_setup_params audio_setup_params = {0}; struct msm_hdmi_audio_codec_rx_data *codec_data = dev_get_drvdata(dai->codec->dev); @@ -200,7 +200,7 @@ static void msm_hdmi_audio_codec_rx_dai_shutdown( struct msm_hdmi_audio_codec_rx_data *codec_data = dev_get_drvdata(dai->codec->dev); - rc = codec_data->hdmi_ops.hdmi_cable_status( + rc = codec_data->hdmi_ops.cable_status( codec_data->hdmi_core_pdev, 0); if (IS_ERR_VALUE(rc)) { dev_err(dai->dev, diff --git a/sound/soc/codecs/wsa881x-regmap.c b/sound/soc/codecs/wsa881x-regmap.c index 5a65846d02a4..63bbbfa6beab 100644 --- a/sound/soc/codecs/wsa881x-regmap.c +++ b/sound/soc/codecs/wsa881x-regmap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -154,30 +154,6 @@ static struct reg_default wsa881x_defaults[] = { {WSA881X_SPKR_STATUS3, 0x00}, }; -/* Default register reset values for WSA881x rev 1.0 or 1.1 */ -static struct reg_sequence wsa881x_rev_1_x[] = { - {WSA881X_INTR_MASK, 0x1F, 0x00}, - {WSA881X_OTP_REG_28, 0xFF, 0x00}, - {WSA881X_OTP_REG_29, 0xFF, 0x00}, - {WSA881X_OTP_REG_30, 0xFF, 0x00}, - {WSA881X_OTP_REG_31, 0xFF, 0x00}, - {WSA881X_TEMP_ADC_CTRL, 0x00, 0x00}, - {WSA881X_ADC_SEL_IBIAS, 0x25, 0x00}, - {WSA881X_SPKR_DRV_GAIN, 0x01, 0x00}, - {WSA881X_SPKR_DAC_CTL, 0x40, 0x00}, - {WSA881X_SPKR_BBM_CTL, 0x00, 0x00}, - {WSA881X_SPKR_MISC_CTL1, 0x80, 0x00}, - {WSA881X_SPKR_MISC_CTL2, 0x00, 0x00}, - {WSA881X_SPKR_BIAS_INT, 0x56, 0x00}, - {WSA881X_SPKR_BIAS_PSRR, 0x54, 0x00}, - {WSA881X_BOOST_PS_CTL, 0xC0, 0x00}, - {WSA881X_BOOST_PRESET_OUT1, 0x77, 0x00}, - {WSA881X_BOOST_LOOP_STABILITY, 0xAD, 0x00}, - {WSA881X_SPKR_PROT_ATEST2, 0x00, 0x00}, - {WSA881X_BONGO_RESRV_REG1, 0x00, 0x00}, - {WSA881X_BONGO_RESRV_REG2, 0x00, 0x00}, -}; - /* Default register reset values for WSA881x rev 2.0 */ static struct reg_sequence wsa881x_rev_2_0[] = { {WSA881X_RESET_CTL, 0x00, 0x00}, @@ -222,26 +198,10 @@ void wsa881x_regmap_defaults(struct regmap *regmap, u8 version) return; } - switch (version) { - case WSA881X_1_X: - regcache_cache_only(regmap, true); - ret = regmap_multi_reg_write(regmap, - wsa881x_rev_1_x, - ARRAY_SIZE(wsa881x_rev_1_x)); - regcache_cache_only(regmap, false); - break; - case WSA881X_2_0: - regcache_cache_only(regmap, true); - ret = regmap_multi_reg_write(regmap, - wsa881x_rev_2_0, - ARRAY_SIZE(wsa881x_rev_2_0)); - regcache_cache_only(regmap, false); - break; - default: - pr_debug("%s: unknown version", __func__); - ret = -EINVAL; - break; - } + regcache_cache_only(regmap, true); + ret = regmap_multi_reg_write(regmap, wsa881x_rev_2_0, + ARRAY_SIZE(wsa881x_rev_2_0)); + regcache_cache_only(regmap, false); if (ret) pr_debug("%s: Failed to update regmap defaults ret= %d\n", diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c index 5047df3cfb2b..e4fec6d79f29 100644 --- a/sound/soc/codecs/wsa881x.c +++ b/sound/soc/codecs/wsa881x.c @@ -177,12 +177,7 @@ static ssize_t wsa881x_codec_version_read(struct snd_info_entry *entry, return -EINVAL; } - if (WSA881X_IS_2_0(wsa881x->version)) - len = snprintf(buffer, sizeof(buffer), - "WSA881X-SOUNDWIRE_2_0\n"); - else - len = snprintf(buffer, sizeof(buffer), - "WSA881X-SOUNDWIRE_1_0\n"); + len = snprintf(buffer, sizeof(buffer), "WSA881X-SOUNDWIRE_2_0\n"); return simple_read_from_buffer(buf, count, &pos, buffer, len); } @@ -453,14 +448,9 @@ static int wsa881x_visense_txfe_ctrl(struct snd_soc_codec *codec, bool enable, __func__, enable, isense1_gain, isense2_gain, vsense_gain); if (enable) { - if (WSA881X_IS_2_0(wsa881x->version)) - regmap_multi_reg_write(wsa881x->regmap, - wsa881x_vi_txfe_en_2_0, - ARRAY_SIZE(wsa881x_vi_txfe_en_2_0)); - else - regmap_multi_reg_write(wsa881x->regmap, - wsa881x_vi_txfe_en, - ARRAY_SIZE(wsa881x_vi_txfe_en)); + regmap_multi_reg_write(wsa881x->regmap, + wsa881x_vi_txfe_en_2_0, + ARRAY_SIZE(wsa881x_vi_txfe_en_2_0)); } else { snd_soc_update_bits(codec, WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x08, 0x08); @@ -787,46 +777,18 @@ static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0xC0, 0x80); - if (WSA881X_IS_2_0(wsa881x->version)) - regmap_multi_reg_write(wsa881x->regmap, - wsa881x_pre_pmu_pa_2_0, - ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0)); - else - regmap_multi_reg_write(wsa881x->regmap, - wsa881x_pre_pmu_pa, - ARRAY_SIZE(wsa881x_pre_pmu_pa)); + regmap_multi_reg_write(wsa881x->regmap, + wsa881x_pre_pmu_pa_2_0, + ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0)); break; case SND_SOC_DAPM_POST_PMU: - if (WSA881X_IS_2_0(wsa881x->version)) { - if (!wsa881x->comp_enable) { - /* - * 1ms delay is needed before change in gain - * as per HW requirement. - */ - usleep_range(1000, 1010); - wsa881x_ramp_pa_gain(codec, G_13P5DB, G_18DB, - 1000); - } - } else { + if (!wsa881x->comp_enable) { /* - * 710us delay is needed after PA enable as per - * HW requirement. + * 1ms delay is needed before change in gain + * as per HW requirement. */ - usleep_range(710, 720); - regmap_multi_reg_write(wsa881x->regmap, - wsa881x_post_pmu_pa, - ARRAY_SIZE(wsa881x_post_pmu_pa)); - if (!wsa881x->comp_enable) { - /* - * 1ms delay is needed before change in gain - * as per HW requirement. - */ - usleep_range(1000, 1010); - wsa881x_ramp_pa_gain(codec, G_12DB, G_13P5DB, - 1000); - } - snd_soc_update_bits(codec, WSA881X_ADC_SEL_IBIAS, - 0x70, 0x40); + usleep_range(1000, 1010); + wsa881x_ramp_pa_gain(codec, G_13P5DB, G_18DB, 1000); } if (wsa881x->visense_enable) { wsa881x_visense_txfe_ctrl(codec, ENABLE, @@ -911,59 +873,37 @@ static void wsa881x_init(struct snd_soc_codec *codec) /* Bring out of digital reset */ snd_soc_update_bits(codec, WSA881X_CDC_RST_CTL, 0x01, 0x01); - if (WSA881X_IS_2_0(wsa881x->version)) { - snd_soc_update_bits(codec, WSA881X_CLOCK_CONFIG, 0x10, 0x10); - snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x02, 0x02); - snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80); - snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06); - snd_soc_update_bits(codec, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00); - snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0xF0, 0x40); - snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0x0E, 0x0E); - snd_soc_update_bits(codec, WSA881X_BOOST_LOOP_STABILITY, - 0x03, 0x03); - snd_soc_update_bits(codec, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14); - snd_soc_update_bits(codec, WSA881X_BOOST_START_CTL, 0x80, 0x80); - snd_soc_update_bits(codec, WSA881X_BOOST_START_CTL, 0x03, 0x00); - snd_soc_update_bits(codec, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, - 0x0C, 0x04); - snd_soc_update_bits(codec, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, - 0x03, 0x00); - if (snd_soc_read(codec, WSA881X_OTP_REG_0)) - snd_soc_update_bits(codec, WSA881X_BOOST_PRESET_OUT1, - 0xF0, 0x70); - snd_soc_update_bits(codec, WSA881X_BOOST_PRESET_OUT2, - 0xF0, 0x30); - snd_soc_update_bits(codec, WSA881X_SPKR_DRV_EN, 0x08, 0x08); - snd_soc_update_bits(codec, WSA881X_BOOST_CURRENT_LIMIT, - 0x0F, 0x08); - snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x30, 0x30); - snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00); - snd_soc_update_bits(codec, WSA881X_OTP_REG_28, 0x3F, 0x3A); - snd_soc_update_bits(codec, WSA881X_BONGO_RESRV_REG1, - 0xFF, 0xB2); - snd_soc_update_bits(codec, WSA881X_BONGO_RESRV_REG2, - 0xFF, 0x05); - } else { - /* Set DAC polarity to Rising */ - snd_soc_update_bits(codec, WSA881X_SPKR_DAC_CTL, 0x02, 0x02); - /* set Bias Ref ctrl to 1.225V */ - snd_soc_update_bits(codec, WSA881X_BIAS_REF_CTRL, 0x07, 0x00); - snd_soc_update_bits(codec, WSA881X_SPKR_BBM_CTL, 0x02, 0x02); - snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x00); - snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL2, 0x07, 0x04); - snd_soc_update_bits(codec, WSA881X_SPKR_BIAS_INT, 0x0F, 0x0F); - snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0xF0, 0x10); - snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0x0F, 0x0E); - snd_soc_update_bits(codec, WSA881X_BOOST_PS_CTL, 0x80, 0x00); + snd_soc_update_bits(codec, WSA881X_CLOCK_CONFIG, 0x10, 0x10); + snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x02, 0x02); + snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80); + snd_soc_update_bits(codec, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06); + snd_soc_update_bits(codec, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00); + snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0xF0, 0x40); + snd_soc_update_bits(codec, WSA881X_SPKR_PA_INT, 0x0E, 0x0E); + snd_soc_update_bits(codec, WSA881X_BOOST_LOOP_STABILITY, + 0x03, 0x03); + snd_soc_update_bits(codec, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14); + snd_soc_update_bits(codec, WSA881X_BOOST_START_CTL, 0x80, 0x80); + snd_soc_update_bits(codec, WSA881X_BOOST_START_CTL, 0x03, 0x00); + snd_soc_update_bits(codec, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, + 0x0C, 0x04); + snd_soc_update_bits(codec, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, + 0x03, 0x00); + if (snd_soc_read(codec, WSA881X_OTP_REG_0)) snd_soc_update_bits(codec, WSA881X_BOOST_PRESET_OUT1, - 0xF0, 0xB0); - snd_soc_update_bits(codec, WSA881X_BOOST_PRESET_OUT2, - 0xF0, 0x30); - snd_soc_update_bits(codec, WSA881X_SPKR_DRV_EN, 0x0F, 0x0C); - snd_soc_update_bits(codec, WSA881X_BOOST_CURRENT_LIMIT, - 0x0F, 0x08); - snd_soc_update_bits(codec, WSA881X_BOOST_ZX_CTL, 0x20, 0x00); - } + 0xF0, 0x70); + snd_soc_update_bits(codec, WSA881X_BOOST_PRESET_OUT2, + 0xF0, 0x30); + snd_soc_update_bits(codec, WSA881X_SPKR_DRV_EN, 0x08, 0x08); + snd_soc_update_bits(codec, WSA881X_BOOST_CURRENT_LIMIT, + 0x0F, 0x08); + snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x30, 0x30); + snd_soc_update_bits(codec, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00); + snd_soc_update_bits(codec, WSA881X_OTP_REG_28, 0x3F, 0x3A); + snd_soc_update_bits(codec, WSA881X_BONGO_RESRV_REG1, + 0xFF, 0xB2); + snd_soc_update_bits(codec, WSA881X_BONGO_RESRV_REG2, + 0xFF, 0x05); } static int32_t wsa881x_resource_acquire(struct snd_soc_codec *codec, @@ -1003,17 +943,10 @@ static int32_t wsa881x_temp_reg_read(struct snd_soc_codec *codec, wsa881x_resource_acquire(codec, ENABLE); - if (WSA881X_IS_2_0(wsa881x->version)) { - snd_soc_update_bits(codec, WSA881X_TADC_VALUE_CTL, 0x01, 0x00); - wsa_temp_reg->dmeas_msb = snd_soc_read(codec, WSA881X_TEMP_MSB); - wsa_temp_reg->dmeas_lsb = snd_soc_read(codec, WSA881X_TEMP_LSB); - snd_soc_update_bits(codec, WSA881X_TADC_VALUE_CTL, 0x01, 0x01); - } else { - wsa_temp_reg->dmeas_msb = snd_soc_read(codec, - WSA881X_TEMP_DOUT_MSB); - wsa_temp_reg->dmeas_lsb = snd_soc_read(codec, - WSA881X_TEMP_DOUT_LSB); - } + snd_soc_update_bits(codec, WSA881X_TADC_VALUE_CTL, 0x01, 0x00); + wsa_temp_reg->dmeas_msb = snd_soc_read(codec, WSA881X_TEMP_MSB); + wsa_temp_reg->dmeas_lsb = snd_soc_read(codec, WSA881X_TEMP_LSB); + snd_soc_update_bits(codec, WSA881X_TADC_VALUE_CTL, 0x01, 0x01); wsa_temp_reg->d1_msb = snd_soc_read(codec, WSA881X_OTP_REG_1); wsa_temp_reg->d1_lsb = snd_soc_read(codec, WSA881X_OTP_REG_2); wsa_temp_reg->d2_msb = snd_soc_read(codec, WSA881X_OTP_REG_3); diff --git a/sound/soc/codecs/wsa881x.h b/sound/soc/codecs/wsa881x.h index 01540df96a81..be234ac0cd07 100644 --- a/sound/soc/codecs/wsa881x.h +++ b/sound/soc/codecs/wsa881x.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,14 +20,6 @@ #define WSA881X_MAX_SWR_PORTS 4 -enum { - WSA881X_1_X = 0, - WSA881X_2_0, -}; - -#define WSA881X_IS_2_0(ver) \ - ((ver == WSA881X_2_0) ? 1 : 0) - extern int wsa881x_set_channel_map(struct snd_soc_codec *codec, u8 *port, u8 num_port, unsigned int *ch_mask, unsigned int *ch_rate); |