diff options
29 files changed, 1061 insertions, 68 deletions
diff --git a/arch/arm/boot/dts/qcom/fg-gen3-batterydata-demo-6000mah.dtsi b/arch/arm/boot/dts/qcom/fg-gen3-batterydata-demo-6000mah.dtsi new file mode 100644 index 000000000000..b107918a8e98 --- /dev/null +++ b/arch/arm/boot/dts/qcom/fg-gen3-batterydata-demo-6000mah.dtsi @@ -0,0 +1,78 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,demo_6000mah { + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,nom-batt-capacity-mah = <6000>; + qcom,batt-id-kohm = <75>; + qcom,battery-beta = <3435>; + qcom,battery-type = "Demo_battery_6000mah"; + qcom,fg-profile-data = [ + 2C 1F 3F FC + E9 03 A1 FD + 58 1D FD F5 + 27 12 2C 14 + 3F 18 FF 22 + 9B 45 A3 52 + 55 00 00 00 + 0E 00 00 00 + 00 00 1C AC + F7 CD 71 B5 + 1A 00 0C 00 + 3C EB 54 E4 + EC 05 7F FA + 76 05 F5 02 + CA F3 82 3A + 2A 09 40 40 + 07 00 05 00 + 58 1F 42 06 + 85 03 35 F4 + 4D 1D 37 F2 + 23 0A 79 15 + B7 18 32 23 + 26 45 72 53 + 55 00 00 00 + 0D 00 00 00 + 00 00 13 CC + 03 00 98 BD + 16 00 00 00 + 3C EB 54 E4 + 9F FC A3 F3 + 0F FC DF FA + FF E5 A9 23 + CB 33 08 33 + 07 10 00 00 + 81 0D 99 45 + 16 00 19 00 + 75 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi index a56e9836784c..14567c3b5010 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi @@ -220,6 +220,7 @@ cell-index = <0>; compatible = "qcom,camera"; reg = <0x0>; + qcom,special-support-sensors = "imx362_gt24c64a"; qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; diff --git a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi index da568fd8979c..36441f9aa15a 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi @@ -184,6 +184,8 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; qcom,eeprom-src = <&eeprom0>; cam_vio-supply = <&pm8998_lvs1>; cam_vana-supply = <&pmi8998_bob>; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..3ef09569a430 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,csiphy@ca34000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csiphy@ca35000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csiphy@ca36000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csid@ca30000 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30400 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30800 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30c00 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3300000 1350000>; + qcom,cam-vreg-max-voltage = <0 3600000 1350000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmfalcon_gpios 4 0>, + <&tlmm 29 0>, + <&tlmm 27 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3300000 1350000>; + qcom,cam-vreg-max-voltage = <0 3600000 1350000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmfalcon_gpios 4 0>, + <&tlmm 29 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pmfalcon_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..3ef09569a430 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,csiphy@ca34000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csiphy@ca35000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csiphy@ca36000 { + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + }; + + qcom,csid@ca30000 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30400 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30800 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; + + qcom,csid@ca30c00 { + qcom,csi-vdd-voltage = <1225000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 27 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3300000 1350000>; + qcom,cam-vreg-max-voltage = <0 3600000 1350000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmfalcon_gpios 4 0>, + <&tlmm 29 0>, + <&tlmm 27 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3300000 1350000>; + qcom,cam-vreg-max-voltage = <0 3600000 1350000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmfalcon_gpios 4 0>, + <&tlmm 29 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pmfalcon_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi index e83191ebfbc0..54a2a4a00dc0 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi @@ -45,12 +45,6 @@ /delete-property/qcom,switch-source; }; -&eeprom0 { - /delete-property/cam_vio-supply; - /delete-property/cam_vana-supply; - /delete-property/cam_vdig-supply; - /delete-property/gpios; -}; &eeprom1 { /delete-property/cam_vio-supply; @@ -66,7 +60,6 @@ }; &cci { - /delete-node/qcom,camera@0; /delete-node/qcom,camera@1; /delete-node/qcom,camera@2; @@ -220,10 +213,6 @@ }; &soc { - /delete-node/qcom,csid@ca30000; - /delete-node/qcom,csid@ca30400; - /delete-node/qcom,csid@ca30800; - /delete-node/qcom,csid@ca30c00; /delete-node/gpio_keys; /delete-node/qcom,lpass@17300000; /delete-node/qcom,mss@4080000; diff --git a/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi index 76124833dc36..45d6398daf25 100644 --- a/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi @@ -623,5 +623,6 @@ qcom,batt-id-range-pct = <15>; #include "fg-gen3-batterydata-itech-3000mah.dtsi" #include "fg-gen3-batterydata-ascent-3450mah.dtsi" + #include "fg-gen3-batterydata-demo-6000mah.dtsi" }; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts index 528e48df1268..bb7046ab58cb 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts @@ -17,6 +17,7 @@ #include "msm8998-interposer-msmfalcon-cdp.dtsi" #include "msm8998-interposer-pmfalcon.dtsi" #include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-interposer-camera-sensor-cdp.dtsi" / { model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer CDP"; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts index 0f0a88b33402..166e09577d46 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts @@ -17,6 +17,7 @@ #include "msm8998-interposer-msmfalcon-mtp.dtsi" #include "msm8998-interposer-pmfalcon.dtsi" #include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-interposer-camera-sensor-mtp.dtsi" / { model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer MTP"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index ed8bee03b4d0..79cdc2b701e1 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -48,6 +48,7 @@ reg = <0x0 0x0>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea0>; }; CPU1: cpu@1 { @@ -56,6 +57,7 @@ reg = <0x0 0x1>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea1>; }; CPU2: cpu@2 { @@ -64,6 +66,7 @@ reg = <0x0 0x2>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea2>; }; CPU3: cpu@3 { @@ -72,6 +75,7 @@ reg = <0x0 0x3>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea3>; }; CPU4: cpu@100 { @@ -80,6 +84,7 @@ reg = <0x0 0x100>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile1>; + qcom,ea = <&ea4>; }; CPU5: cpu@101 { @@ -88,6 +93,7 @@ reg = <0x0 0x101>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile2>; + qcom,ea = <&ea5>; }; CPU6: cpu@102 { @@ -96,6 +102,7 @@ reg = <0x0 0x102>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile3>; + qcom,ea = <&ea6>; }; CPU7: cpu@103 { @@ -104,6 +111,7 @@ reg = <0x0 0x103>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile4>; + qcom,ea = <&ea7>; }; cpu-map { @@ -540,6 +548,45 @@ }; }; + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + qcom,low-hyst-temp = <10>; + qcom,high-hyst-temp = <5>; + + ea0: ea0 { + sensor = <&sensor_information1>; + }; + + ea1: ea1 { + sensor = <&sensor_information1>; + }; + + ea2: ea2 { + sensor = <&sensor_information1>; + }; + + ea3: ea3 { + sensor = <&sensor_information1>; + }; + + ea4: ea4 { + sensor = <&sensor_information3>; + }; + + ea5: ea5 { + sensor = <&sensor_information4>; + }; + + ea6: ea6 { + sensor = <&sensor_information5>; + }; + + ea7: ea7 { + sensor = <&sensor_information6>; + }; + }; + uartblsp2dm1: serial@0c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; @@ -1206,6 +1253,34 @@ qcom,irq-is-percpu; interrupts = <1 6 4>; }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0x2200000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 200000 400000>, + <55 512 300000 800000>, + <55 512 400000 1000000>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc QSEECOM_CE1_CLK>, + <&clock_gcc QSEECOM_CE1_CLK>, + <&clock_gcc QSEECOM_CE1_CLK>, + <&clock_gcc QSEECOM_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; }; #include "msmfalcon-ion.dtsi" diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c index 55c043b44cea..0bef7effe601 100644 --- a/drivers/crypto/msm/qce50.c +++ b/drivers/crypto/msm/qce50.c @@ -1347,7 +1347,8 @@ go_proc: CRYPTO_CONFIG_REG)); /* issue go to crypto */ if (use_hw_key == false) { - QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), pce_dev->iobase + CRYPTO_GOPROC_REG); } else { QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), @@ -1528,7 +1529,8 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev, CRYPTO_CONFIG_REG)); /* issue go to crypto */ - QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), pce_dev->iobase + CRYPTO_GOPROC_REG); /* * Ensure previous instructions (setting the GO register) @@ -1847,7 +1849,8 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev, CRYPTO_CONFIG_REG)); /* issue go to crypto */ if (use_hw_key == false) { - QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), pce_dev->iobase + CRYPTO_GOPROC_REG); } else { QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), @@ -1935,7 +1938,8 @@ static int _ce_f9_setup_direct(struct qce_device *pce_dev, QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + CRYPTO_CONFIG_REG)); /* write go */ - QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), pce_dev->iobase + CRYPTO_GOPROC_REG); /* * Ensure previous instructions (setting the GO register) @@ -2012,7 +2016,8 @@ static int _ce_f8_setup_direct(struct qce_device *pce_dev, QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + CRYPTO_CONFIG_REG)); /* write go */ - QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), pce_dev->iobase + CRYPTO_GOPROC_REG); /* * Ensure previous instructions (setting the GO register) @@ -3336,8 +3341,8 @@ static int _setup_cipher_aes_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -3450,8 +3455,8 @@ static int _setup_cipher_des_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -3494,8 +3499,8 @@ static int _setup_cipher_null_cmdlistptrs(struct qce_device *pdev, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -3672,8 +3677,8 @@ static int _setup_auth_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -3889,8 +3894,8 @@ static int _setup_aead_cmdlistptrs(struct qce_device *pdev, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -4022,8 +4027,8 @@ static int _setup_aead_ccm_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -4108,8 +4113,8 @@ static int _setup_f8_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; @@ -4190,8 +4195,8 @@ static int _setup_f9_cmdlistptrs(struct qce_device *pdev, int cri_index, pdev->reg.crypto_cfg_le, NULL); qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, - ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), - &pcl_info->go_proc); + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; *pvaddr = (unsigned char *) ce_vaddr; diff --git a/drivers/gpu/msm/adreno_a5xx_preempt.c b/drivers/gpu/msm/adreno_a5xx_preempt.c index 09c550c9f58c..0e56731b16e2 100644 --- a/drivers/gpu/msm/adreno_a5xx_preempt.c +++ b/drivers/gpu/msm/adreno_a5xx_preempt.c @@ -22,7 +22,7 @@ #define PREEMPT_SMMU_RECORD(_field) \ offsetof(struct a5xx_cp_smmu_info, _field) -static void _update_wptr(struct adreno_device *adreno_dev) +static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) { struct adreno_ringbuffer *rb = adreno_dev->cur_rb; unsigned int wptr; @@ -35,10 +35,16 @@ static void _update_wptr(struct adreno_device *adreno_dev) if (wptr != rb->wptr) { adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR, rb->wptr); + /* + * In case something got submitted while preemption was on + * going, reset the timer. + */ + reset_timer = 1; + } + if (reset_timer) rb->dispatch_q.expires = jiffies + msecs_to_jiffies(adreno_drawobj_timeout); - } spin_unlock_irqrestore(&rb->preempt_lock, flags); } @@ -90,7 +96,7 @@ static void _a5xx_preemption_done(struct adreno_device *adreno_dev) adreno_dev->next_rb = NULL; /* Update the wptr for the new command queue */ - _update_wptr(adreno_dev); + _update_wptr(adreno_dev, true); /* Update the dispatcher timer for the new command queue */ mod_timer(&adreno_dev->dispatcher.timer, @@ -213,7 +219,7 @@ void a5xx_preemption_trigger(struct adreno_device *adreno_dev) */ if (next != NULL) { - _update_wptr(adreno_dev); + _update_wptr(adreno_dev, false); mod_timer(&adreno_dev->dispatcher.timer, adreno_dev->cur_rb->dispatch_q.expires); @@ -304,7 +310,7 @@ void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit) adreno_dev->next_rb = NULL; /* Update the wptr if it changed while preemption was ongoing */ - _update_wptr(adreno_dev); + _update_wptr(adreno_dev, true); /* Update the dispatcher timer for the new command queue */ mod_timer(&adreno_dev->dispatcher.timer, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h index 3b6a2eecb4b6..13a7a398759b 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h @@ -243,6 +243,8 @@ struct msm_vfe_core_ops { bool (*is_module_cfg_lock_needed)(uint32_t reg_offset); int (*ahb_clk_cfg)(struct vfe_device *vfe_dev, struct msm_isp_ahb_clk_cfg *ahb_cfg); + int (*start_fetch_eng_multi_pass)(struct vfe_device *vfe_dev, + void *arg); }; struct msm_vfe_stats_ops { int (*get_stats_idx)(enum msm_isp_stats_type stats_type); @@ -774,7 +776,7 @@ struct vfe_device { struct msm_isp_statistics *stats; uint64_t msm_isp_last_overflow_ab; uint64_t msm_isp_last_overflow_ib; - uint64_t msm_isp_vfe_clk_rate; + uint32_t msm_isp_vfe_clk_rate; struct msm_isp_ub_info *ub_info; uint32_t isp_sof_debug; uint32_t isp_raw0_debug; diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c index 96f9e61578f2..1375d3ce8c65 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c @@ -1054,11 +1054,72 @@ static int msm_vfe40_start_fetch_engine(struct vfe_device *vfe_dev, return 0; } +static int msm_vfe40_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, + void *arg) +{ + int rc = 0; + uint32_t bufq_handle = 0; + struct msm_isp_buffer *buf = NULL; + struct msm_vfe_fetch_eng_multi_pass_start *fe_cfg = arg; + struct msm_isp_buffer_mapped_info mapped_info; + + if (vfe_dev->fetch_engine_info.is_busy == 1) { + pr_err("%s: fetch engine busy\n", __func__); + return -EINVAL; + } + memset(&mapped_info, 0, sizeof(struct msm_isp_buffer_mapped_info)); + /* There is other option of passing buffer address from user, + * in such case, driver needs to map the buffer and use it + */ + vfe_dev->fetch_engine_info.session_id = fe_cfg->session_id; + vfe_dev->fetch_engine_info.stream_id = fe_cfg->stream_id; + vfe_dev->fetch_engine_info.offline_mode = fe_cfg->offline_mode; + vfe_dev->fetch_engine_info.fd = fe_cfg->fd; + + if (!fe_cfg->offline_mode) { + bufq_handle = vfe_dev->buf_mgr->ops->get_bufq_handle( + vfe_dev->buf_mgr, fe_cfg->session_id, + fe_cfg->stream_id); + vfe_dev->fetch_engine_info.bufq_handle = bufq_handle; + + rc = vfe_dev->buf_mgr->ops->get_buf_by_index( + vfe_dev->buf_mgr, bufq_handle, fe_cfg->buf_idx, &buf); + if (rc < 0 || !buf) { + pr_err("%s: No fetch buffer rc= %d buf= %p\n", + __func__, rc, buf); + return -EINVAL; + } + mapped_info = buf->mapped_info[0]; + buf->state = MSM_ISP_BUFFER_STATE_DISPATCHED; + } else { + rc = vfe_dev->buf_mgr->ops->map_buf(vfe_dev->buf_mgr, + &mapped_info, fe_cfg->fd); + if (rc < 0) { + pr_err("%s: can not map buffer\n", __func__); + return -EINVAL; + } + } + vfe_dev->fetch_engine_info.buf_idx = fe_cfg->buf_idx; + vfe_dev->fetch_engine_info.is_busy = 1; + + msm_camera_io_w(mapped_info.paddr + fe_cfg->input_buf_offset, + vfe_dev->vfe_base + 0x228); + + msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x378); + + msm_camera_io_w_mb(0x10000, vfe_dev->vfe_base + 0x4C); + msm_camera_io_w_mb(0x20000, vfe_dev->vfe_base + 0x4C); + + ISP_DBG("%s:VFE%d Fetch Engine ready\n", __func__, vfe_dev->pdev->id); + return 0; +} + static void msm_vfe40_cfg_fetch_engine(struct vfe_device *vfe_dev, struct msm_vfe_pix_cfg *pix_cfg) { uint32_t x_size_word; uint32_t temp = 0; + uint32_t main_unpack_pattern = 0; struct msm_vfe_fetch_engine_cfg *fe_cfg = NULL; if (pix_cfg->input_mux != EXTERNAL_READ) { @@ -1089,10 +1150,14 @@ static void msm_vfe40_cfg_fetch_engine(struct vfe_device *vfe_dev, /* need to update to use formulae to calculate X_SIZE_WORD*/ x_size_word = msm_isp_cal_word_per_line( vfe_dev->axi_data.src_info[VFE_PIX_0].input_format, - fe_cfg->fetch_width); + fe_cfg->buf_width); msm_camera_io_w((x_size_word - 1) << 16, vfe_dev->vfe_base + 0x23C); + x_size_word = msm_isp_cal_word_per_line( + vfe_dev->axi_data.src_info[VFE_PIX_0].input_format, + fe_cfg->fetch_width); + temp = msm_camera_io_r(vfe_dev->vfe_base + 0x1C); temp |= 2 << 16 | pix_cfg->pixel_pattern; msm_camera_io_w(temp, vfe_dev->vfe_base + 0x1C); @@ -1118,7 +1183,19 @@ static void msm_vfe40_cfg_fetch_engine(struct vfe_device *vfe_dev, } /* need to use formulae to calculate MAIN_UNPACK_PATTERN*/ - msm_camera_io_w(0xF6543210, vfe_dev->vfe_base + 0x248); + switch (vfe_dev->axi_data.src_info[VFE_PIX_0].input_format) { + case V4L2_PIX_FMT_P16BGGR10: + case V4L2_PIX_FMT_P16GBRG10: + case V4L2_PIX_FMT_P16GRBG10: + case V4L2_PIX_FMT_P16RGGB10: + main_unpack_pattern = 0xB210; + break; + default: + main_unpack_pattern = 0xF6543210; + break; + } + msm_camera_io_w(main_unpack_pattern, + vfe_dev->vfe_base + 0x248); msm_camera_io_w(0xF, vfe_dev->vfe_base + 0x264); return; @@ -2261,6 +2338,8 @@ struct msm_vfe_hardware_info vfe40_hw_info = { .is_module_cfg_lock_needed = msm_vfe40_is_module_cfg_lock_needed, .ahb_clk_cfg = NULL, + .start_fetch_eng_multi_pass = + msm_vfe40_start_fetch_engine_multi_pass, }, .stats_ops = { .get_stats_idx = msm_vfe40_get_stats_idx, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c index c50c55a69fb5..98e73d48ad15 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c @@ -1077,11 +1077,70 @@ int msm_vfe47_start_fetch_engine(struct vfe_device *vfe_dev, return 0; } +int msm_vfe47_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, + void *arg) +{ + int rc = 0; + uint32_t bufq_handle = 0; + struct msm_isp_buffer *buf = NULL; + struct msm_vfe_fetch_eng_multi_pass_start *fe_cfg = arg; + struct msm_isp_buffer_mapped_info mapped_info; + + if (vfe_dev->fetch_engine_info.is_busy == 1) { + pr_err("%s: fetch engine busy\n", __func__); + return -EINVAL; + } + + memset(&mapped_info, 0, sizeof(struct msm_isp_buffer_mapped_info)); + + vfe_dev->fetch_engine_info.session_id = fe_cfg->session_id; + vfe_dev->fetch_engine_info.stream_id = fe_cfg->stream_id; + vfe_dev->fetch_engine_info.offline_mode = fe_cfg->offline_mode; + vfe_dev->fetch_engine_info.fd = fe_cfg->fd; + + if (!fe_cfg->offline_mode) { + bufq_handle = vfe_dev->buf_mgr->ops->get_bufq_handle( + vfe_dev->buf_mgr, fe_cfg->session_id, + fe_cfg->stream_id); + vfe_dev->fetch_engine_info.bufq_handle = bufq_handle; + + rc = vfe_dev->buf_mgr->ops->get_buf_by_index( + vfe_dev->buf_mgr, bufq_handle, fe_cfg->buf_idx, &buf); + if (rc < 0 || !buf) { + pr_err("%s: No fetch buffer rc= %d buf= %pK\n", + __func__, rc, buf); + return -EINVAL; + } + mapped_info = buf->mapped_info[0]; + buf->state = MSM_ISP_BUFFER_STATE_DISPATCHED; + } else { + rc = vfe_dev->buf_mgr->ops->map_buf(vfe_dev->buf_mgr, + &mapped_info, fe_cfg->fd); + if (rc < 0) { + pr_err("%s: can not map buffer\n", __func__); + return -EINVAL; + } + } + + vfe_dev->fetch_engine_info.buf_idx = fe_cfg->buf_idx; + vfe_dev->fetch_engine_info.is_busy = 1; + + msm_camera_io_w(mapped_info.paddr + fe_cfg->input_buf_offset, + vfe_dev->vfe_base + 0x2F4); + msm_camera_io_w_mb(0x100000, vfe_dev->vfe_base + 0x80); + msm_camera_io_w_mb(0x200000, vfe_dev->vfe_base + 0x80); + + ISP_DBG("%s:VFE%d Fetch Engine ready\n", __func__, vfe_dev->pdev->id); + + return 0; +} + void msm_vfe47_cfg_fetch_engine(struct vfe_device *vfe_dev, struct msm_vfe_pix_cfg *pix_cfg) { uint32_t x_size_word, temp; struct msm_vfe_fetch_engine_cfg *fe_cfg = NULL; + uint32_t main_unpack_pattern = 0; if (pix_cfg->input_mux == EXTERNAL_READ) { fe_cfg = &pix_cfg->fetch_engine_cfg; @@ -1107,10 +1166,13 @@ void msm_vfe47_cfg_fetch_engine(struct vfe_device *vfe_dev, x_size_word = msm_isp_cal_word_per_line( vfe_dev->axi_data.src_info[VFE_PIX_0].input_format, - fe_cfg->fetch_width); + fe_cfg->buf_width); msm_camera_io_w((x_size_word - 1) << 16, vfe_dev->vfe_base + 0x30c); + x_size_word = msm_isp_cal_word_per_line( + vfe_dev->axi_data.src_info[VFE_PIX_0].input_format, + fe_cfg->fetch_width); msm_camera_io_w(x_size_word << 16 | (temp & 0x3FFF) << 2 | VFE47_FETCH_BURST_LEN, vfe_dev->vfe_base + 0x310); @@ -1120,7 +1182,19 @@ void msm_vfe47_cfg_fetch_engine(struct vfe_device *vfe_dev, msm_camera_io_w(temp, vfe_dev->vfe_base + 0x314); /* need to use formulae to calculate MAIN_UNPACK_PATTERN*/ - msm_camera_io_w(0xF6543210, vfe_dev->vfe_base + 0x318); + switch (vfe_dev->axi_data.src_info[VFE_PIX_0].input_format) { + case V4L2_PIX_FMT_P16BGGR10: + case V4L2_PIX_FMT_P16GBRG10: + case V4L2_PIX_FMT_P16GRBG10: + case V4L2_PIX_FMT_P16RGGB10: + main_unpack_pattern = 0xB210; + break; + default: + main_unpack_pattern = 0xF6543210; + break; + } + msm_camera_io_w(main_unpack_pattern, + vfe_dev->vfe_base + 0x318); msm_camera_io_w(0xF, vfe_dev->vfe_base + 0x334); temp = msm_camera_io_r(vfe_dev->vfe_base + 0x50); @@ -2721,6 +2795,8 @@ struct msm_vfe_hardware_info vfe47_hw_info = { .is_module_cfg_lock_needed = msm_vfe47_is_module_cfg_lock_needed, .ahb_clk_cfg = msm_isp47_ahb_clk_cfg, + .start_fetch_eng_multi_pass = + msm_vfe47_start_fetch_engine_multi_pass, }, .stats_ops = { .get_stats_idx = msm_vfe47_get_stats_idx, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h index 3955196d1deb..6524ac84edf3 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h @@ -65,6 +65,8 @@ int32_t msm_vfe47_cfg_io_format(struct vfe_device *vfe_dev, enum msm_vfe_axi_stream_src stream_src, uint32_t io_format); int msm_vfe47_start_fetch_engine(struct vfe_device *vfe_dev, void *arg); +int msm_vfe47_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, + void *arg); void msm_vfe47_cfg_fetch_engine(struct vfe_device *vfe_dev, struct msm_vfe_pix_cfg *pix_cfg); void msm_vfe47_cfg_testgen(struct vfe_device *vfe_dev, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c index 49520bb44ad8..568125e2d7c2 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c @@ -309,6 +309,8 @@ struct msm_vfe_hardware_info vfe48_hw_info = { .is_module_cfg_lock_needed = msm_vfe47_is_module_cfg_lock_needed, .ahb_clk_cfg = msm_isp47_ahb_clk_cfg, + .start_fetch_eng_multi_pass = + msm_vfe47_start_fetch_engine_multi_pass, }, .stats_ops = { .get_stats_idx = msm_vfe47_get_stats_idx, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c index e8289f05d28f..3b9c3c9d3926 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c @@ -1691,6 +1691,76 @@ static struct msm_isp_buffer *msm_isp_get_stream_buffer( return buf; } +int msm_isp_cfg_offline_ping_pong_address(struct vfe_device *vfe_dev, + struct msm_vfe_axi_stream *stream_info, uint32_t pingpong_status, + uint32_t buf_idx) +{ + int i, rc = 0; + struct msm_isp_buffer *buf = NULL; + uint32_t pingpong_bit; + uint32_t buffer_size_byte = 0; + int32_t word_per_line = 0; + dma_addr_t paddr; + uint32_t bufq_handle = 0; + int vfe_idx; + + bufq_handle = stream_info->bufq_handle[VFE_BUF_QUEUE_DEFAULT]; + + if (!vfe_dev->is_split) { + rc = vfe_dev->buf_mgr->ops->get_buf_by_index( + vfe_dev->buf_mgr, bufq_handle, buf_idx, &buf); + if (rc < 0 || !buf) { + pr_err("%s: No fetch buffer rc= %d buf= %p\n", + __func__, rc, buf); + return -EINVAL; + } + + if (buf->num_planes != stream_info->num_planes) { + pr_err("%s: Invalid buffer\n", __func__); + vfe_dev->buf_mgr->ops->put_buf(vfe_dev->buf_mgr, + bufq_handle, buf->buf_idx); + return -EINVAL; + } + vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev, stream_info); + pingpong_bit = ((pingpong_status >> + stream_info->wm[vfe_idx][0]) & 0x1); + + for (i = 0; i < stream_info->num_planes; i++) { + word_per_line = msm_isp_cal_word_per_line( + stream_info->output_format, + stream_info->plane_cfg[vfe_idx][i]. + output_stride); + if (word_per_line < 0) { + /* 0 means no prefetch*/ + word_per_line = 0; + buffer_size_byte = 0; + } else { + buffer_size_byte = (word_per_line * 8 * + stream_info->plane_cfg[vfe_idx][i]. + output_scan_lines) - + stream_info-> + plane_cfg[vfe_idx][i].plane_addr_offset; + } + paddr = buf->mapped_info[i].paddr; + + vfe_dev->hw_info->vfe_ops.axi_ops. + update_ping_pong_addr( + vfe_dev->vfe_base, stream_info->wm[vfe_idx][i], + pingpong_bit, paddr + + stream_info-> + plane_cfg[vfe_idx][i].plane_addr_offset, + buffer_size_byte); + stream_info->buf[!pingpong_bit] = buf; + buf->pingpong_bit = !pingpong_bit; + } + buf->state = MSM_ISP_BUFFER_STATE_DEQUEUED; + stream_info->buf[!pingpong_bit] = buf; + buf->pingpong_bit = !pingpong_bit; + } + return rc; + +} + static int msm_isp_cfg_ping_pong_address( struct msm_vfe_axi_stream *stream_info, uint32_t pingpong_status) { @@ -1888,6 +1958,11 @@ static int msm_isp_process_done_buf(struct vfe_device *vfe_dev, buf_event.u.buf_done.buf_idx = buf->buf_idx; buf_event.u.buf_done.output_format = stream_info->runtime_output_format; + if (vfe_dev->fetch_engine_info.is_busy && + SRC_TO_INTF(stream_info->stream_src) == VFE_PIX_0) { + vfe_dev->fetch_engine_info.is_busy = 0; + } + if (stream_info->buf_divert && buf_src != MSM_ISP_BUFFER_SRC_SCRATCH) { @@ -2065,7 +2140,8 @@ static void msm_isp_input_enable(struct vfe_device *vfe_dev, continue; /* activate the input since it is deactivated */ axi_data->src_info[i].frame_id = 0; - axi_data->src_info[i].active = 1; + if (axi_data->src_info[i].input_mux != EXTERNAL_READ) + axi_data->src_info[i].active = 1; if (i >= VFE_RAW_0 && sync_frame_id_src) { /* * Incase PIX and RDI streams are part @@ -3534,6 +3610,7 @@ int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) unsigned long flags; struct msm_isp_timestamp timestamp; uint32_t frame_id; + int vfe_idx; /*num_stream is uint32 and update_info[] bound by MAX_NUM_STREAM*/ if (update_cmd->num_streams > MAX_NUM_STREAM) @@ -3746,6 +3823,20 @@ int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) __func__); break; } + case UPDATE_STREAM_OFFLINE_AXI_CONFIG: { + for (i = 0; i < update_cmd->num_streams; i++) { + update_info = + (struct msm_vfe_axi_stream_cfg_update_info *) + &update_cmd->update_info[i]; + stream_info = msm_isp_get_stream_common_data(vfe_dev, + HANDLE_TO_IDX(update_info->stream_handle)); + vfe_idx = msm_isp_get_vfe_idx_for_stream( + vfe_dev, stream_info); + msm_isp_stream_axi_cfg_update(vfe_dev, stream_info, + update_info); + } + break; + } default: pr_err("%s: Invalid update type %d\n", __func__, update_cmd->update_type); diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h index 9c642370b1a1..f9ae5fb74281 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h @@ -157,4 +157,7 @@ static inline struct msm_vfe_axi_stream *msm_isp_vfe_get_stream( index); } +int msm_isp_cfg_offline_ping_pong_address(struct vfe_device *vfe_dev, + struct msm_vfe_axi_stream *stream_info, uint32_t pingpong_status, + uint32_t buf_idx); #endif /* __MSM_ISP_AXI_UTIL_H__ */ diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c index b0789ce4a71c..72eac5d81627 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c @@ -375,6 +375,47 @@ static int msm_isp_start_fetch_engine(struct vfe_device *vfe_dev, start_fetch_eng(vfe_dev, arg); } +static int msm_isp_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, + void *arg) +{ + struct msm_vfe_fetch_eng_multi_pass_start *fe_cfg = arg; + struct msm_vfe_axi_stream *stream_info = NULL; + int i = 0, rc; + uint32_t wm_reload_mask = 0; + int vfe_idx; + /* + * For Offline VFE, HAL expects same frame id + * for offline output which it requested in do_reprocess. + */ + vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id = + fe_cfg->frame_id; + if (fe_cfg->offline_pass == OFFLINE_SECOND_PASS) { + stream_info = msm_isp_get_stream_common_data(vfe_dev, + HANDLE_TO_IDX(fe_cfg->output_stream_id)); + if (stream_info == NULL) { + pr_err("%s: Error in Offline process\n", __func__); + return -EINVAL; + } + vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev, stream_info); + msm_isp_reset_framedrop(vfe_dev, stream_info); + + rc = msm_isp_cfg_offline_ping_pong_address(vfe_dev, stream_info, + VFE_PING_FLAG, fe_cfg->output_buf_idx); + if (rc < 0) { + pr_err("%s: Fetch engine config failed\n", __func__); + return -EINVAL; + } + for (i = 0; i < stream_info->num_planes; i++) + wm_reload_mask |= (1 << stream_info->wm[vfe_idx][i]); + vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, + VFE_SRC_MAX); + vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev, + vfe_dev->vfe_base, wm_reload_mask); + } + return vfe_dev->hw_info->vfe_ops.core_ops. + start_fetch_eng_multi_pass(vfe_dev, arg); +} + void msm_isp_fetch_engine_done_notify(struct vfe_device *vfe_dev, struct msm_vfe_fetch_engine_info *fetch_engine_info) { @@ -880,6 +921,13 @@ static long msm_isp_ioctl_unlocked(struct v4l2_subdev *sd, rc = msm_isp_start_fetch_engine(vfe_dev, arg); mutex_unlock(&vfe_dev->core_mutex); break; + + case VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START: + case VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE: + mutex_lock(&vfe_dev->core_mutex); + rc = msm_isp_start_fetch_engine_multi_pass(vfe_dev, arg); + mutex_unlock(&vfe_dev->core_mutex); + break; case VIDIOC_MSM_ISP_REG_UPDATE_CMD: if (arg) { enum msm_vfe_input_src frame_src = diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c index ab074ffbcdfb..b9018a226f2f 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c +++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c @@ -3031,8 +3031,7 @@ STREAM_BUFF_END: uint32_t identity; struct msm_cpp_buff_queue_info_t *buff_queue_info; CPP_DBG("VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO\n"); - if ((ioctl_ptr->len == 0) || - (ioctl_ptr->len > sizeof(uint32_t))) { + if (ioctl_ptr->len != sizeof(uint32_t)) { mutex_unlock(&cpp_dev->mutex); return -EINVAL; } diff --git a/drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c b/drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c index b1c23823c122..f113bdc5de01 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c +++ b/drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c @@ -115,15 +115,16 @@ static int32_t msm_cci_set_clk_param(struct cci_device *cci_dev, enum cci_i2c_master_t master = c_ctrl->cci_info->cci_i2c_master; enum i2c_freq_mode_t i2c_freq_mode = c_ctrl->cci_info->i2c_freq_mode; - clk_params = &cci_dev->cci_clk_params[i2c_freq_mode]; - if ((i2c_freq_mode >= I2C_MAX_MODES) || (i2c_freq_mode < 0)) { pr_err("%s:%d invalid i2c_freq_mode = %d", __func__, __LINE__, i2c_freq_mode); return -EINVAL; } + if (cci_dev->i2c_freq_mode[master] == i2c_freq_mode) return 0; + + clk_params = &cci_dev->cci_clk_params[i2c_freq_mode]; if (MASTER_0 == master) { msm_camera_io_w_mb(clk_params->hw_thigh << 16 | clk_params->hw_tlow, @@ -1196,6 +1197,13 @@ static uint32_t *msm_cci_get_clk_rates(struct cci_device *cci_dev, struct msm_cci_clk_params_t *clk_params = NULL; enum i2c_freq_mode_t i2c_freq_mode = c_ctrl->cci_info->i2c_freq_mode; struct device_node *of_node = cci_dev->pdev->dev.of_node; + + if ((i2c_freq_mode >= I2C_MAX_MODES) || (i2c_freq_mode < 0)) { + pr_err("%s:%d invalid i2c_freq_mode %d\n", + __func__, __LINE__, i2c_freq_mode); + return NULL; + } + clk_params = &cci_dev->cci_clk_params[i2c_freq_mode]; cci_clk_src = clk_params->cci_clk_src; diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index bf854a3140b2..d445f95924ef 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -3128,6 +3128,11 @@ irqreturn_t mdss_dsi_isr(int irq, void *ptr) pr_debug("%s: ndx=%d isr=%x\n", __func__, ctrl->ndx, isr); + if (isr & DSI_INTR_ERROR) { + MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x97); + mdss_dsi_error(ctrl); + } + if (isr & DSI_INTR_BTA_DONE) { MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x96); spin_lock(&ctrl->mdp_lock); @@ -3152,11 +3157,6 @@ irqreturn_t mdss_dsi_isr(int irq, void *ptr) spin_unlock(&ctrl->mdp_lock); } - if (isr & DSI_INTR_ERROR) { - MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x97); - mdss_dsi_error(ctrl); - } - if (isr & DSI_INTR_VIDEO_DONE) { spin_lock(&ctrl->mdp_lock); mdss_dsi_disable_irq_nosync(ctrl, DSI_VIDEO_TERM); diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index 3dfcbfb291ef..e137a8b050b0 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -1816,8 +1816,10 @@ static int mdss_mdp_debug_init(struct platform_device *pdev, mdss_debug_register_dump_range(pdev, dbg_blk, "qcom,regs-dump-mdp", "qcom,regs-dump-names-mdp", "qcom,regs-dump-xin-id-mdp"); - mdss_debug_register_io("vbif", &mdata->vbif_io, NULL); - mdss_debug_register_io("vbif_nrt", &mdata->vbif_nrt_io, NULL); + if (mdata->vbif_io.base) + mdss_debug_register_io("vbif", &mdata->vbif_io, NULL); + if (mdata->vbif_nrt_io.base) + mdss_debug_register_io("vbif_nrt", &mdata->vbif_nrt_io, NULL); return 0; } diff --git a/drivers/video/fbdev/msm/mdss_mdp_ctl.c b/drivers/video/fbdev/msm/mdss_mdp_ctl.c index 169095f64a0f..9c5c5ea090c3 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_ctl.c +++ b/drivers/video/fbdev/msm/mdss_mdp_ctl.c @@ -5495,8 +5495,13 @@ int mdss_mdp_ctl_update_fps(struct mdss_mdp_ctl *ctl) (pinfo->dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP) || (pinfo->dfps_update == DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP) || + (pinfo->dfps_update == + DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK) || pinfo->dfps_update == DFPS_IMMEDIATE_CLK_UPDATE_MODE) { - new_fps = mdss_panel_get_framerate(pinfo); + if (pinfo->type == DTV_PANEL) + new_fps = pinfo->lcdc.frame_rate; + else + new_fps = mdss_panel_get_framerate(pinfo); } else { new_fps = pinfo->new_fps; } diff --git a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c index fabdc5cd3e42..5d5515a91572 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c +++ b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c @@ -1424,7 +1424,9 @@ static int mdss_mdp_video_config_fps(struct mdss_mdp_ctl *ctl, int new_fps) pdata->panel_info.dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP || pdata->panel_info.dfps_update - == DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP) { + == DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP || + pdata->panel_info.dfps_update + == DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK) { unsigned long flags; if (!ctx->timegen_en) { pr_err("TG is OFF. DFPS mode invalid\n"); diff --git a/drivers/video/fbdev/msm/mdss_mdp_overlay.c b/drivers/video/fbdev/msm/mdss_mdp_overlay.c index 0203c0e69e3f..154b9d86e67c 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_overlay.c +++ b/drivers/video/fbdev/msm/mdss_mdp_overlay.c @@ -3064,16 +3064,23 @@ static void cache_initial_timings(struct mdss_panel_data *pdata) * This value will change dynamically once the * actual dfps update happen in hw. */ - pdata->panel_info.current_fps = - mdss_panel_get_framerate(&pdata->panel_info); - + if (pdata->panel_info.type == DTV_PANEL) + pdata->panel_info.current_fps = + pdata->panel_info.lcdc.frame_rate; + else + pdata->panel_info.current_fps = + mdss_panel_get_framerate(&pdata->panel_info); /* * Keep the initial fps and porch values for this panel before * any dfps update happen, this is to prevent losing precision * in further calculations. */ - pdata->panel_info.default_fps = - mdss_panel_get_framerate(&pdata->panel_info); + if (pdata->panel_info.type == DTV_PANEL) + pdata->panel_info.default_fps = + pdata->panel_info.lcdc.frame_rate; + else + pdata->panel_info.default_fps = + mdss_panel_get_framerate(&pdata->panel_info); if (pdata->panel_info.dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP) { @@ -3085,7 +3092,9 @@ static void cache_initial_timings(struct mdss_panel_data *pdata) } else if (pdata->panel_info.dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP || pdata->panel_info.dfps_update == - DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP) { + DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP || + pdata->panel_info.dfps_update == + DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK) { pdata->panel_info.saved_total = mdss_panel_get_htotal(&pdata->panel_info, true); pdata->panel_info.saved_fporch = @@ -3154,8 +3163,25 @@ static void dfps_update_panel_params(struct mdss_panel_data *pdata, pdata->panel_info.lcdc.h_pulse_width = data->hpw; pdata->panel_info.clk_rate = data->clk_rate; + if (pdata->panel_info.type == DTV_PANEL) + pdata->panel_info.clk_rate *= 1000; + + dfps_update_fps(&pdata->panel_info, new_fps); + } else if (pdata->panel_info.dfps_update == + DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK) { + + pr_debug("hfp=%d, hbp=%d, hpw=%d, clk=%d, fps=%d\n", + data->hfp, data->hbp, data->hpw, + data->clk_rate, data->fps); + + pdata->panel_info.lcdc.h_front_porch = data->hfp; + pdata->panel_info.lcdc.h_back_porch = data->hbp; + pdata->panel_info.lcdc.h_pulse_width = data->hpw; + + pdata->panel_info.clk_rate = data->clk_rate; dfps_update_fps(&pdata->panel_info, new_fps); + mdss_panel_update_clk_rate(&pdata->panel_info, new_fps); } else { dfps_update_fps(&pdata->panel_info, new_fps); mdss_panel_update_clk_rate(&pdata->panel_info, new_fps); @@ -3230,7 +3256,9 @@ static ssize_t dynamic_fps_sysfs_wta_dfps(struct device *dev, } if (pdata->panel_info.dfps_update == - DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP) { + DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP || + pdata->panel_info.dfps_update == + DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK) { if (sscanf(buf, "%u %u %u %u %u", &data.hfp, &data.hbp, &data.hpw, &data.clk_rate, &data.fps) != 5) { @@ -3245,7 +3273,10 @@ static ssize_t dynamic_fps_sysfs_wta_dfps(struct device *dev, } } - panel_fps = mdss_panel_get_framerate(&pdata->panel_info); + if (pdata->panel_info.type == DTV_PANEL) + panel_fps = pdata->panel_info.lcdc.frame_rate; + else + panel_fps = mdss_panel_get_framerate(&pdata->panel_info); if (data.fps == panel_fps) { pr_debug("%s: FPS is already %d\n", @@ -3308,7 +3339,7 @@ static ssize_t mdss_mdp_lineptr_show_event(struct device *dev, if (!mdp5_data->ctl || (!mdp5_data->ctl->panel_data->panel_info.cont_splash_enabled && !mdss_mdp_ctl_is_power_on(mdp5_data->ctl))) - return -EAGAIN; + return -EPERM; lineptr_ticks = ktime_to_ns(mdp5_data->lineptr_time); @@ -3329,7 +3360,7 @@ static ssize_t mdss_mdp_lineptr_show_value(struct device *dev, if (!mdp5_data->ctl || (!mdp5_data->ctl->panel_data->panel_info.cont_splash_enabled && !mdss_mdp_ctl_is_power_on(mdp5_data->ctl))) - return -EAGAIN; + return -EPERM; lineptr_val = mfd->panel_info->te.wr_ptr_irq; diff --git a/drivers/video/fbdev/msm/mdss_panel.h b/drivers/video/fbdev/msm/mdss_panel.h index 25ae326ebbc3..16bb48e22bee 100644 --- a/drivers/video/fbdev/msm/mdss_panel.h +++ b/drivers/video/fbdev/msm/mdss_panel.h @@ -540,7 +540,10 @@ struct dynamic_fps_data { * @DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP: update fps using vertical timings * @DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP: update fps using horizontal timings * @DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP: update fps using both horizontal - * timings and clock. + * timings and clock. + * @DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK: update fps using both + * horizontal timings, clock need to be caculate base on new clock and + * porches. * @DFPS_MODE_MAX: defines maximum limit of supported modes. */ enum dynamic_fps_update { @@ -549,6 +552,7 @@ enum dynamic_fps_update { DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP, DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP, DFPS_IMMEDIATE_MULTI_UPDATE_MODE_CLK_HFP, + DFPS_IMMEDIATE_MULTI_MODE_HFP_CALC_CLK, DFPS_MODE_MAX }; @@ -978,7 +982,9 @@ static inline u32 mdss_panel_get_framerate(struct mdss_panel_info *panel_info) break; case DTV_PANEL: if (panel_info->dynamic_fps) { - frame_rate = panel_info->lcdc.frame_rate; + frame_rate = panel_info->lcdc.frame_rate / 1000; + if (panel_info->lcdc.frame_rate % 1000) + frame_rate += 1; break; } default: diff --git a/include/uapi/media/msmb_isp.h b/include/uapi/media/msmb_isp.h index cdb85170919a..e4d41d4072c5 100644 --- a/include/uapi/media/msmb_isp.h +++ b/include/uapi/media/msmb_isp.h @@ -261,6 +261,26 @@ struct msm_vfe_fetch_eng_start { uint32_t frame_id; }; +enum msm_vfe_fetch_eng_pass { + OFFLINE_FIRST_PASS, + OFFLINE_SECOND_PASS, + OFFLINE_MAX_PASS, +}; + +struct msm_vfe_fetch_eng_multi_pass_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint8_t offline_mode; + uint32_t fd; + uint32_t buf_addr; + uint32_t frame_id; + uint32_t output_buf_idx; + uint32_t input_buf_offset; + enum msm_vfe_fetch_eng_pass offline_pass; + uint32_t output_stream_id; +}; + struct msm_vfe_axi_plane_cfg { uint32_t output_width; /*Include padding*/ uint32_t output_height; @@ -328,6 +348,7 @@ enum msm_vfe_axi_stream_update_type { UPDATE_STREAM_REMOVE_BUFQ, UPDATE_STREAM_SW_FRAME_DROP, UPDATE_STREAM_REQUEST_FRAMES_VER2, + UPDATE_STREAM_OFFLINE_AXI_CONFIG, }; #define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 @@ -853,6 +874,8 @@ enum msm_isp_ioctl_cmd_code { MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, MSM_ISP_MAP_BUF_START_FE, MSM_ISP_UNMAP_BUF, + MSM_ISP_FETCH_ENG_MULTI_PASS_START, + MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, }; #define VIDIOC_MSM_VFE_REG_CFG \ @@ -958,4 +981,11 @@ enum msm_isp_ioctl_cmd_code { #define VIDIOC_MSM_ISP_AHB_CLK_CFG \ _IOWR('V', BASE_VIDIOC_PRIVATE+25, struct msm_isp_ahb_clk_cfg) +#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \ + _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \ + struct msm_vfe_fetch_eng_multi_pass_start) + +#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \ + _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \ + struct msm_vfe_fetch_eng_multi_pass_start) #endif /* __MSMB_ISP__ */ |