diff options
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi | 12 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-sim.dts | 12 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi | 27 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 35 |
4 files changed, 45 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi index 7ced6a33f8f4..06bce23ddf31 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi @@ -20,21 +20,29 @@ reg = <0x1da7000 0xda8>, /* PHY regs */ <0x1db8000 0x100>; /* U11 user regs */ reg-names = "phy_mem", "u11_user"; - vdda-phy-supply = <&pmcobalt_l28>; + vdda-phy-supply = <&pmcobalt_l1>; vdda-pll-supply = <&pmcobalt_l2>; vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; status = "ok"; }; &ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; vcc-supply = <&pmcobalt_l20>; vccq-supply = <&pmcobalt_l26>; vccq2-supply = <&pmcobalt_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; qcom,disable-lpm; rpm-level = <0>; spm-level = <0>; - status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts b/arch/arm/boot/dts/qcom/msmcobalt-sim.dts index 0adfaefe69f2..69c047994c98 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts +++ b/arch/arm/boot/dts/qcom/msmcobalt-sim.dts @@ -33,18 +33,6 @@ qcom,xo-clk-rate = <19200000>; }; -&ufsphy1 { - status = "ok"; -}; - -&ufs1 { - status = "ok"; -}; - -&ufs_ice { - status = "ok"; -}; - &qusb_phy0 { compatible = "usb-nop-xceiv"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi index 2d7027034efd..475a37dc4229 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi @@ -18,6 +18,33 @@ pinctrl-0 = <&uart_console_active>; }; +&ufsphy1 { + vdda-phy-supply = <&pmcobalt_l1>; + vdda-pll-supply = <&pmcobalt_l2>; + vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pmcobalt_l20>; + vccq-supply = <&pmcobalt_l26>; + vccq2-supply = <&pmcobalt_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + &sdhc_2 { vdd-supply = <&pmcobalt_l21>; qcom,vdd-voltage-level = <2950000 2960000>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 63bcec04cf8e..f04291d41c95 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -1079,14 +1079,12 @@ reg = <0x1da7000 0xda8>; reg-names = "phy_mem"; #phy-cells = <0>; - vdda-phy-max-microamp = <51430>; - vdda-pll-max-microamp = <14170>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; clock-names = "ref_clk_src", - "ref_clk"; + "ref_clk", + "ref_aux_clk"; clocks = <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_ufs_clkref_clk>; + <&clock_gcc clk_gcc_ufs_clkref_clk>, + <&clock_gcc clk_gcc_ufs_phy_aux_clk>; status = "disabled"; }; @@ -1094,24 +1092,18 @@ compatible = "qcom,ice"; reg = <0x1db0000 0x8000>; qcom,enable-ice-clk; - clock-names = "ufs_core_clk_src", - "ufs_core_clk", + clock-names = "ufs_core_clk", "bus_clk", "iface_clk", - "ice_core_clk_src", "ice_core_clk"; - clocks = <&clock_gcc clk_ufs_axi_clk_src>, - <&clock_gcc clk_gcc_ufs_axi_clk>, + clocks = <&clock_gcc clk_gcc_ufs_axi_clk>, <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, <&clock_gcc clk_gcc_ufs_ahb_clk>, - <&clock_gcc clk_ufs_ice_core_clk_src>, <&clock_gcc clk_gcc_ufs_ice_core_clk>; qcom,op-freq-hz = <0>, <0>, <0>, - <0>, - <300000000>, - <0>; + <300000000>; vdd-hba-supply = <&gdsc_ufs>; qcom,msm-bus,name = "ufs_ice_noc"; qcom,msm-bus,num-cases = <2>; @@ -1131,30 +1123,21 @@ interrupts = <0 265 0>; phys = <&ufsphy1>; phy-names = "ufsphy"; - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-max-microamp = <750000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <750000>; ufs-qcom-crypto = <&ufs_ice>; clock-names = - "core_clk_src", "core_clk", "bus_aggr_clk", "iface_clk", - "core_clk_unipro_src", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; clocks = - <&clock_gcc clk_ufs_axi_clk_src>, <&clock_gcc clk_gcc_ufs_axi_clk>, <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, <&clock_gcc clk_gcc_ufs_ahb_clk>, - <&clock_gcc clk_ufs_ice_core_clk_src>, <&clock_gcc clk_gcc_ufs_unipro_core_clk>, <&clock_gcc clk_gcc_ufs_ice_core_clk>, <&clock_gcc clk_ln_bb_clk1>, @@ -1164,12 +1147,10 @@ <100000000 200000000>, <0 0>, <0 0>, - <0 0>, + <75000000 150000000>, <150000000 300000000>, <0 0>, <0 0>, - <0 0>, - <0 0>, <0 0>; lanes-per-direction = <1>; |