diff options
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi.h | 9 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_phy_v3.c | 30 |
2 files changed, 36 insertions, 3 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi.h b/drivers/video/fbdev/msm/mdss_dsi.h index ecffc12ecd72..bd1854092c6a 100644 --- a/drivers/video/fbdev/msm/mdss_dsi.h +++ b/drivers/video/fbdev/msm/mdss_dsi.h @@ -920,10 +920,17 @@ static inline enum dsi_logical_lane_id mdss_dsi_physical_to_logical_lane( static inline enum dsi_physical_lane_id mdss_dsi_logical_to_physical_lane( struct mdss_dsi_ctrl_pdata *ctrl, enum dsi_logical_lane_id id) { + int i; + if (id >= DSI_LOGICAL_LANE_MAX) return DSI_PHYSICAL_LANE_INVALID; - return ctrl->lane_map[id]; + for (i = DSI_LOGICAL_LANE_0; i < DSI_LOGICAL_LANE_MAX; i++) { + if (BIT(i) == ctrl->lane_map[id]) + break; + } + + return i; } #endif /* MDSS_DSI_H */ diff --git a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c index 9f419c91661c..9033d1b9e643 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c +++ b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c @@ -160,6 +160,25 @@ static void mdss_dsi_phy_v3_config_timings(struct mdss_dsi_ctrl_pdata *ctrl) } } +static void mdss_dsi_phy_v3_config_lpcdrx(struct mdss_dsi_ctrl_pdata *ctrl, + bool enable) +{ + struct mdss_dsi_phy_ctrl *pd = + &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); + enum dsi_physical_lane_id phy_lane_0 = + mdss_dsi_logical_to_physical_lane(ctrl, DSI_LOGICAL_LANE_0); + + /* + * LPRX and CDRX need to enabled only for physical data lane + * corresponding to the logical data lane 0 + */ + if (enable) + DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(phy_lane_0), + pd->strength[(phy_lane_0 * 2) + 1]); + else + DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(phy_lane_0), 0); +} + static void mdss_dsi_phy_v3_config_lane_settings( struct mdss_dsi_ctrl_pdata *ctrl) { @@ -172,11 +191,17 @@ static void mdss_dsi_phy_v3_config_lane_settings( for (i = 0; i < 5; i++) { DSI_PHY_W32(ctrl->phy_io.base, LNX_LPTX_STR_CTRL(i), pd->strength[(i * 2)]); - DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i), - pd->strength[(i * 2) + 1]); + /* + * Disable LPRX and CDRX for all lanes. And later on, it will + * be only enabled for the physical data lane corresponding + * to the logical data lane 0 + */ + DSI_PHY_W32(ctrl->phy_io.base, LNX_LPRX_CTRL(i), 0); + DSI_PHY_W32(ctrl->phy_io.base, LNX_HSTX_STR_CTRL(i), 0x88); DSI_PHY_W32(ctrl->phy_io.base, LNX_PIN_SWAP(i), 0x0); } + mdss_dsi_phy_v3_config_lpcdrx(ctrl, true); /* Other settings */ for (i = 0; i < 5; i++) { @@ -306,6 +331,7 @@ int mdss_dsi_phy_v3_shutdown(struct mdss_dsi_ctrl_pdata *ctrl) if (mdss_dsi_phy_v3_is_pll_on(ctrl)) pr_warn("Disabling phy with PLL still enabled\n"); + mdss_dsi_phy_v3_config_lpcdrx(ctrl, false); mdss_dsi_phy_v3_lanes_disable(ctrl); /* Turn off all PHY blocks */ |