summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/usb/msm-phy.txt33
-rw-r--r--Documentation/devicetree/bindings/usb/msm-ssusb.txt7
-rw-r--r--arch/arm/boot/dts/qcom/msm8996.dtsi27
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt.dtsi21
-rw-r--r--drivers/usb/dwc3/dwc3-msm.c34
-rw-r--r--drivers/usb/phy/phy-msm-qusb-v2.c38
-rw-r--r--drivers/usb/phy/phy-msm-qusb.c20
-rw-r--r--drivers/usb/phy/phy-msm-ssusb-qmp.c81
8 files changed, 158 insertions, 103 deletions
diff --git a/Documentation/devicetree/bindings/usb/msm-phy.txt b/Documentation/devicetree/bindings/usb/msm-phy.txt
index 0af26ca1f380..b45ee910258e 100644
--- a/Documentation/devicetree/bindings/usb/msm-phy.txt
+++ b/Documentation/devicetree/bindings/usb/msm-phy.txt
@@ -118,6 +118,10 @@ Required properties:
USB3_PHY_POWER_DOWN_CONTROL,
USB3_PHY_SW_RESET,
USB3_PHY_START
+- resets: reset specifier pair consists of phandle for the reset controller
+ and reset lines used by this controller.
+- reset-names: reset signal name strings sorted in the same order as the resets
+ property.
Optional properties:
- reg: Additional register set of address and length to control QMP PHY are:
@@ -126,7 +130,7 @@ Optional properties:
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
- property. Required clocks are "cfg_ahb_clk", "phy_reset" and "phy_phy_reset".
+ property. "cfg_ahb_clk" is an optional clock.
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
the USB PHY and the controller must rely on external VBUS notification in
order to manually relay the notification to the SSPHY.
@@ -150,13 +154,17 @@ Example:
clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
<&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
- <&clock_gcc clk_gcc_usb3_phy_reset>,
- <&clock_gcc clk_gcc_usb3phy_phy_reset>,
<&clock_gcc clk_ln_bb_clk1>,
<&clock_gcc clk_gcc_usb3_clkref_clk>;
- clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
- "phy_phy_reset", "ref_clk_src", "ref_clk";
+ clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
+ "ref_clk_src", "ref_clk";
+
+ resets = <&clock_gcc GCC_USB3_PHY_BCR>,
+ <&clock_gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy_reset",
+ "phy_phy_reset";
+
};
QUSB2 High-Speed PHY
@@ -173,11 +181,11 @@ Required properties:
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
- - clocks: a list of phandles to the PHY clocks. Use as per
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
- property. Required clock is "phy_reset".
- phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
+ - resets: reset specifier pair consists of phandle for the reset controller
+ and reset lines used by this controller.
+ - reset-names: reset signal name strings sorted in the same order as the resets
+ property.
Optional properties:
- reg-names: Additional registers corresponding with the following:
@@ -218,7 +226,8 @@ Example:
clocks = <&clock_rpm clk_ln_bb_clk>,
<&clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
- <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
- <&clock_gcc clk_gcc_qusb2_phy_reset>;
- clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";
+ <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
+ clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk";
+ resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
};
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
index c5e5f1851fc2..f4d10908f4ff 100644
--- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -15,6 +15,10 @@ Required properties :
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk"
and "utmi_clk".
+- resets: reset specifier pair consists of phandle for the reset provider
+ and reset lines used by this controller.
+- reset-names: reset signal name strings sorted in the same order as the resets
+ property.
Optional properties :
- reg: Additional registers
@@ -99,6 +103,9 @@ Example MSM USB3.0 controller device node :
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
+ resets = <&clock_gcc GCC_USB_30_BCR>;
+ reset-names = "core_reset";
+
dwc3@f9200000 {
compatible = "synopsys,dwc3";
reg = <0xf9200000 0xfc000>;
diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi
index aa973e4ee3d6..e0d84e423e88 100644
--- a/arch/arm/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996.dtsi
@@ -1934,6 +1934,9 @@
clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk",
"sleep_clk", "xo", "cfg_ahb_clk";
+ resets = <&clock_gcc USB_30_BCR>;
+ reset-names = "core_reset";
+
dwc3@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xc8d0>;
@@ -2039,6 +2042,8 @@
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
"xo", "cfg_ahb_clk";
+ resets = <&clock_gcc USB_20_BCR>;
+ reset-names = "core_reset";
dwc3@7600000 {
compatible = "snps,dwc3";
@@ -2088,10 +2093,11 @@
qcom,major-rev = <1>;
clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
- <&clock_gcc clk_gcc_qusb2phy_prim_reset>,
<&clock_gcc clk_ln_bb_clk>;
+ clock-names = "cfg_ahb_clk", "ref_clk_src";
- clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src";
+ resets = <&clock_gcc QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
};
qusb_phy1: qusb@7412000 {
@@ -2124,10 +2130,11 @@
qcom,hold-reset;
clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
- <&clock_gcc clk_gcc_qusb2phy_sec_reset>,
- <&clock_gcc clk_ln_bb_clk>;
+ <&clock_gcc clk_ln_bb_clk>;
+ clock-names = "cfg_ahb_clk", "ref_clk_src";
- clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src";
+ resets = <&clock_gcc QUSB2PHY_SEC_BCR>;
+ reset-names = "phy_reset";
};
ssphy: ssphy@7410000 {
@@ -2209,13 +2216,15 @@
clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
<&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
- <&clock_gcc clk_gcc_usb3_phy_reset>,
- <&clock_gcc clk_gcc_usb3phy_phy_reset>,
<&clock_gcc clk_ln_bb_clk>,
<&clock_gcc clk_gcc_usb3_clkref_clk>;
- clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
- "phy_phy_reset", "ref_clk_src", "ref_clk";
+ clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
+ "ref_clk_src", "ref_clk";
+
+ resets = <&clock_gcc USB3_PHY_BCR>,
+ <&clock_gcc USB3PHY_PHY_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
};
usb_nop_phy: usb_nop_phy {
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 4ea1cf31c4dc..a4d4b706eef7 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -1804,6 +1804,10 @@
"utmi_clk", "sleep_clk", "xo";
qcom,core-clk-rate = <120000000>;
+
+ resets = <&clock_gcc USB_30_BCR>;
+ reset-names = "core_reset";
+
dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
@@ -1870,10 +1874,11 @@
phy_type= "utmi";
clocks = <&clock_gcc clk_ln_bb_clk1>,
- <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>,
- <&clock_gcc clk_gcc_qusb2phy_prim_reset>;
+ <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>;
+ clock-names = "ref_clk_src", "ref_clk";
- clock-names = "ref_clk_src", "ref_clk", "phy_reset";
+ resets = <&clock_gcc QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
};
ssphy: ssphy@c010000 {
@@ -2021,13 +2026,15 @@
clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
<&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
- <&clock_gcc clk_gcc_usb3_phy_reset>,
- <&clock_gcc clk_gcc_usb3phy_phy_reset>,
<&clock_gcc clk_ln_bb_clk1>,
<&clock_gcc clk_gcc_usb3_clkref_clk>;
- clock-names = "aux_clk", "pipe_clk", "phy_reset",
- "phy_phy_reset", "ref_clk_src", "ref_clk";
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "ref_clk";
+
+ resets = <&clock_gcc USB3_PHY_BCR>,
+ <&clock_gcc USB3PHY_PHY_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
};
usb_audio_qmi_dev {
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 8189096f95c2..f24816f06a5b 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -45,6 +45,7 @@
#include <linux/msm-bus.h>
#include <linux/irq.h>
#include <linux/extcon.h>
+#include <linux/reset.h>
#include "power.h"
#include "core.h"
@@ -159,6 +160,7 @@ struct dwc3_msm {
struct clk *utmi_clk_src;
struct clk *bus_aggr_clk;
struct clk *cfg_ahb_clk;
+ struct reset_control *core_reset;
struct regulator *dwc3_gdsc;
struct usb_phy *hs_phy, *ss_phy;
@@ -1517,19 +1519,19 @@ static int dwc3_msm_link_clk_reset(struct dwc3_msm *mdwc, bool assert)
clk_disable_unprepare(mdwc->sleep_clk);
clk_disable_unprepare(mdwc->core_clk);
clk_disable_unprepare(mdwc->iface_clk);
- ret = clk_reset(mdwc->core_clk, CLK_RESET_ASSERT);
+ ret = reset_control_assert(mdwc->core_reset);
if (ret)
- dev_err(mdwc->dev, "dwc3 core_clk assert failed\n");
+ dev_err(mdwc->dev, "dwc3 core_reset assert failed\n");
} else {
dev_dbg(mdwc->dev, "block_reset DEASSERT\n");
- ret = clk_reset(mdwc->core_clk, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(mdwc->core_reset);
+ if (ret)
+ dev_err(mdwc->dev, "dwc3 core_reset deassert failed\n");
ndelay(200);
clk_prepare_enable(mdwc->iface_clk);
clk_prepare_enable(mdwc->core_clk);
clk_prepare_enable(mdwc->sleep_clk);
clk_prepare_enable(mdwc->utmi_clk);
- if (ret)
- dev_err(mdwc->dev, "dwc3 core_clk deassert failed\n");
enable_irq(mdwc->pwr_event_irq);
}
@@ -2041,11 +2043,16 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc)
if (mdwc->lpm_flags & MDWC3_POWER_COLLAPSE) {
dev_dbg(mdwc->dev, "%s: exit power collapse\n", __func__);
dwc3_msm_config_gdsc(mdwc, 1);
-
- clk_reset(mdwc->core_clk, CLK_RESET_ASSERT);
+ ret = reset_control_assert(mdwc->core_reset);
+ if (ret)
+ dev_err(mdwc->dev, "%s:core_reset assert failed\n",
+ __func__);
/* HW requires a short delay for reset to take place properly */
usleep_range(1000, 1200);
- clk_reset(mdwc->core_clk, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(mdwc->core_reset);
+ if (ret)
+ dev_err(mdwc->dev, "%s:core_reset deassert failed\n",
+ __func__);
clk_prepare_enable(mdwc->sleep_clk);
}
@@ -2366,6 +2373,17 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc)
mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, LONG_MAX);
}
+ mdwc->core_reset = devm_reset_control_get(mdwc->dev, "core_reset");
+ if (IS_ERR(mdwc->core_reset)) {
+ dev_err(mdwc->dev, "failed to get core_reset\n");
+ return PTR_ERR(mdwc->core_reset);
+ }
+
+ /*
+ * Get Max supported clk frequency for USB Core CLK and request
+ * to set the same.
+ */
+ mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, LONG_MAX);
if (IS_ERR_VALUE(mdwc->core_clk_rate)) {
dev_err(mdwc->dev, "fail to get core clk max freq.\n");
} else {
diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c
index b222c3c5f7b4..4ecdc350fbd4 100644
--- a/drivers/usb/phy/phy-msm-qusb-v2.c
+++ b/drivers/usb/phy/phy-msm-qusb-v2.c
@@ -27,6 +27,7 @@
#include <linux/regulator/machine.h>
#include <linux/usb/phy.h>
#include <linux/usb/msm_hsusb.h>
+#include <linux/reset.h>
#define QUSB2PHY_PWR_CTRL1 0x210
#define PWR_CTRL1_POWR_DOWN BIT(0)
@@ -76,7 +77,7 @@ struct qusb_phy {
struct clk *ref_clk_src;
struct clk *ref_clk;
struct clk *cfg_ahb_clk;
- struct clk *phy_reset;
+ struct reset_control *phy_reset;
struct regulator *vdd;
struct regulator *vdda33;
@@ -370,14 +371,19 @@ static void qusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt,
static void qusb_phy_host_init(struct usb_phy *phy)
{
u8 reg;
+ int ret;
struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy);
dev_dbg(phy->dev, "%s\n", __func__);
/* Perform phy reset */
- clk_reset(qphy->phy_reset, CLK_RESET_ASSERT);
+ ret = reset_control_assert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset assert failed\n", __func__);
usleep_range(100, 150);
- clk_reset(qphy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset deassert failed\n", __func__);
qusb_phy_write_seq(qphy->base, qphy->qusb_phy_host_init_seq,
qphy->host_init_seq_len, 0);
@@ -411,9 +417,13 @@ static int qusb_phy_init(struct usb_phy *phy)
qusb_phy_enable_clocks(qphy, true);
/* Perform phy reset */
- clk_reset(qphy->phy_reset, CLK_RESET_ASSERT);
+ ret = reset_control_assert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset assert failed\n", __func__);
usleep_range(100, 150);
- clk_reset(qphy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset deassert failed\n", __func__);
if (qphy->emulation) {
if (qphy->emu_init_seq)
@@ -531,6 +541,7 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend)
{
struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy);
u32 linestate = 0, intr_mask = 0;
+ int ret;
if (qphy->suspended && suspend) {
dev_dbg(phy->dev, "%s: USB PHY is already suspended\n",
@@ -578,9 +589,15 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend)
qusb_phy_enable_clocks(qphy, false);
} else { /* Cable disconnect case */
- clk_reset(qphy->phy_reset, CLK_RESET_ASSERT);
+ ret = reset_control_assert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset assert failed\n",
+ __func__);
usleep_range(100, 150);
- clk_reset(qphy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset deassert failed\n",
+ __func__);
/* enable clock bypass */
writel_relaxed(0x90,
@@ -622,7 +639,10 @@ static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend)
*/
wmb();
- clk_reset(qphy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset deassert failed\n",
+ __func__);
qusb_phy_enable_power(qphy, true, true);
qusb_phy_enable_clocks(qphy, true);
@@ -802,7 +822,7 @@ static int qusb_phy_probe(struct platform_device *pdev)
}
}
- qphy->phy_reset = devm_clk_get(dev, "phy_reset");
+ qphy->phy_reset = devm_reset_control_get(dev, "phy_reset");
if (IS_ERR(qphy->phy_reset))
return PTR_ERR(qphy->phy_reset);
diff --git a/drivers/usb/phy/phy-msm-qusb.c b/drivers/usb/phy/phy-msm-qusb.c
index af7ec03314f5..5456b9e8733b 100644
--- a/drivers/usb/phy/phy-msm-qusb.c
+++ b/drivers/usb/phy/phy-msm-qusb.c
@@ -27,6 +27,7 @@
#include <linux/regulator/machine.h>
#include <linux/usb/phy.h>
#include <linux/usb/msm_hsusb.h>
+#include <linux/reset.h>
#define QUSB2PHY_PLL_STATUS 0x38
#define QUSB2PHY_PLL_LOCK BIT(5)
@@ -112,7 +113,7 @@ struct qusb_phy {
struct clk *ref_clk_src;
struct clk *ref_clk;
struct clk *cfg_ahb_clk;
- struct clk *phy_reset;
+ struct reset_control *phy_reset;
struct regulator *vdd;
struct regulator *vdda33;
@@ -443,9 +444,13 @@ static int qusb_phy_init(struct usb_phy *phy)
}
/* Perform phy reset */
- clk_reset(qphy->phy_reset, CLK_RESET_ASSERT);
+ ret = reset_control_assert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset assert failed\n", __func__);
usleep_range(100, 150);
- clk_reset(qphy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret)
+ dev_err(phy->dev, "%s: phy_reset deassert failed\n", __func__);
if (qphy->emulation) {
if (qphy->emu_init_seq)
@@ -858,7 +863,7 @@ static int qusb_phy_probe(struct platform_device *pdev)
if (IS_ERR(qphy->cfg_ahb_clk))
return PTR_ERR(qphy->cfg_ahb_clk);
- qphy->phy_reset = devm_clk_get(dev, "phy_reset");
+ qphy->phy_reset = devm_reset_control_get(dev, "phy_reset");
if (IS_ERR(qphy->phy_reset))
return PTR_ERR(qphy->phy_reset);
@@ -1011,8 +1016,11 @@ static int qusb_phy_probe(struct platform_device *pdev)
* not used, there is leakage current seen with QUSB PHY related voltage
* rail. Hence keep QUSB PHY into reset state explicitly here.
*/
- if (hold_phy_reset)
- clk_reset(qphy->phy_reset, CLK_RESET_ASSERT);
+ if (hold_phy_reset) {
+ ret = reset_control_assert(qphy->phy_reset);
+ if (ret)
+ dev_err(dev, "%s:phy_reset assert failed\n", __func__);
+ }
ret = usb_add_phy_dev(&qphy->phy);
if (ret)
diff --git a/drivers/usb/phy/phy-msm-ssusb-qmp.c b/drivers/usb/phy/phy-msm-ssusb-qmp.c
index 87235a5a4f99..fc61e3172d0b 100644
--- a/drivers/usb/phy/phy-msm-ssusb-qmp.c
+++ b/drivers/usb/phy/phy-msm-ssusb-qmp.c
@@ -25,6 +25,7 @@
#include <linux/usb/msm_hsusb.h>
#include <linux/clk.h>
#include <linux/clk/msm-clk.h>
+#include <linux/reset.h>
enum core_ldo_levels {
CORE_LEVEL_NONE = 0,
@@ -87,9 +88,10 @@ struct msm_ssphy_qmp {
struct clk *aux_clk;
struct clk *cfg_ahb_clk;
struct clk *pipe_clk;
- struct clk *phy_reset;
- struct clk *phy_phy_reset;
bool power_enabled;
+ struct reset_control *phy_reset;
+ struct reset_control *phy_phy_reset;
+
bool clk_enabled;
bool cable_connected;
bool in_suspend;
@@ -371,56 +373,39 @@ static int msm_ssphy_qmp_reset(struct usb_phy *uphy)
dev_dbg(uphy->dev, "Resetting QMP phy\n");
/* Assert USB3 PHY reset */
- if (phy->phy_phy_reset) {
- ret = clk_reset(phy->phy_phy_reset, CLK_RESET_ASSERT);
- if (ret) {
- dev_err(uphy->dev, "phy_phy reset assert failed\n");
- goto exit;
- }
- } else {
- ret = clk_reset(phy->pipe_clk, CLK_RESET_ASSERT);
- if (ret) {
- dev_err(uphy->dev, "pipe_clk reset assert failed\n");
- goto exit;
- }
+ ret = reset_control_assert(phy->phy_phy_reset);
+ if (ret) {
+ dev_err(uphy->dev, "phy_phy_reset assert failed\n");
+ goto exit;
}
/* Assert USB3 PHY CSR reset */
- ret = clk_reset(phy->phy_reset, CLK_RESET_ASSERT);
+ ret = reset_control_assert(phy->phy_reset);
if (ret) {
- dev_err(uphy->dev, "phy_reset clk assert failed\n");
+ dev_err(uphy->dev, "phy_reset assert failed\n");
goto deassert_phy_phy_reset;
}
/* Deassert USB3 PHY CSR reset */
- ret = clk_reset(phy->phy_reset, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(phy->phy_reset);
if (ret) {
- dev_err(uphy->dev, "phy_reset clk deassert failed\n");
+ dev_err(uphy->dev, "phy_reset deassert failed\n");
goto deassert_phy_phy_reset;
}
/* Deassert USB3 PHY reset */
- if (phy->phy_phy_reset) {
- ret = clk_reset(phy->phy_phy_reset, CLK_RESET_DEASSERT);
- if (ret) {
- dev_err(uphy->dev, "phy_phy reset deassert failed\n");
- goto exit;
- }
- } else {
- ret = clk_reset(phy->pipe_clk, CLK_RESET_DEASSERT);
- if (ret) {
- dev_err(uphy->dev, "pipe_clk reset deassert failed\n");
- goto exit;
- }
+ ret = reset_control_deassert(phy->phy_phy_reset);
+ if (ret) {
+ dev_err(uphy->dev, "phy_phy_reset deassert failed\n");
+ goto exit;
}
return 0;
deassert_phy_phy_reset:
- if (phy->phy_phy_reset)
- clk_reset(phy->phy_phy_reset, CLK_RESET_DEASSERT);
- else
- clk_reset(phy->pipe_clk, CLK_RESET_DEASSERT);
+ ret = reset_control_deassert(phy->phy_phy_reset);
+ if (ret)
+ dev_err(uphy->dev, "phy_phy_reset deassert failed\n");
exit:
phy->in_suspend = false;
@@ -594,26 +579,18 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
goto err;
}
- if (of_property_match_string(pdev->dev.of_node,
- "clock-names", "phy_reset") >= 0) {
- phy->phy_reset = clk_get(&pdev->dev, "phy_reset");
- if (IS_ERR(phy->phy_reset)) {
- ret = PTR_ERR(phy->phy_reset);
- phy->phy_reset = NULL;
- dev_dbg(dev, "failed to get phy_reset\n");
- goto err;
- }
+ phy->phy_reset = devm_reset_control_get(dev, "phy_reset");
+ if (IS_ERR(phy->phy_reset)) {
+ ret = PTR_ERR(phy->phy_reset);
+ dev_dbg(dev, "failed to get phy_reset\n");
+ goto err;
}
- if (of_property_match_string(pdev->dev.of_node,
- "clock-names", "phy_phy_reset") >= 0) {
- phy->phy_phy_reset = clk_get(dev, "phy_phy_reset");
- if (IS_ERR(phy->phy_phy_reset)) {
- ret = PTR_ERR(phy->phy_phy_reset);
- phy->phy_phy_reset = NULL;
- dev_dbg(dev, "phy_phy_reset unavailable\n");
- goto err;
- }
+ phy->phy_phy_reset = devm_reset_control_get(dev, "phy_phy_reset");
+ if (IS_ERR(phy->phy_phy_reset)) {
+ ret = PTR_ERR(phy->phy_phy_reset);
+ dev_dbg(dev, "failed to get phy_phy_reset\n");
+ goto err;
}
of_get_property(dev->of_node, "qcom,qmp-phy-reg-offset", &size);
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-02 06:57:23 +0000