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| -rw-r--r-- | Documentation/devicetree/bindings/arm/cache.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt index b27cedf485f8..a9594f026506 100644 --- a/Documentation/devicetree/bindings/arm/cache.txt +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches. bindings of power controller specified by the phandle [5]. + - qcom,dump-size + Usage: Optional + Value type: <integer> + Definition: The memory size needed to contain a copy of the + cache data and associated tag ram. + size = nways * nsets * (bytes per cache line + + bytes tag ram per line) + Example(dual-cluster big.LITTLE system 32-bit) cpus { |