diff options
| -rw-r--r-- | drivers/clk/msm/clock-mmss-cobalt.c | 56 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-hwio-cobalt.h | 2 |
3 files changed, 56 insertions, 4 deletions
diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c index ba9196b7abc9..777571bb7c96 100644 --- a/drivers/clk/msm/clock-mmss-cobalt.c +++ b/drivers/clk/msm/clock-mmss-cobalt.c @@ -1746,13 +1746,36 @@ static struct branch_clk mmss_mdss_byte0_clk = { }, }; +static struct div_clk mmss_mdss_byte0_intf_div_clk = { + .offset = MMSS_MDSS_BYTE0_INTF_DIV, + .mask = 0x3, + .shift = 0, + .data = { + .min_div = 1, + .max_div = 4, + }, + .base = &virt_base, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .ops = &postdiv_reg_ops, + .c = { + .dbg_name = "mmss_mdss_byte0_intf_div_clk", + .parent = &byte0_clk_src.c, + .ops = &clk_ops_slave_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(mmss_mdss_byte0_intf_div_clk.c), + }, +}; + static struct branch_clk mmss_mdss_byte0_intf_clk = { .cbcr_reg = MMSS_MDSS_BYTE0_INTF_CBCR, - .has_sibling = 1, + .has_sibling = 0, .base = &virt_base, .c = { .dbg_name = "mmss_mdss_byte0_intf_clk", - .parent = &byte0_clk_src.c, + .parent = &mmss_mdss_byte0_intf_div_clk.c, .ops = &clk_ops_branch, CLK_INIT(mmss_mdss_byte0_intf_clk.c), }, @@ -1770,13 +1793,36 @@ static struct branch_clk mmss_mdss_byte1_clk = { }, }; +static struct div_clk mmss_mdss_byte1_intf_div_clk = { + .offset = MMSS_MDSS_BYTE1_INTF_DIV, + .mask = 0x3, + .shift = 0, + .data = { + .min_div = 1, + .max_div = 4, + }, + .base = &virt_base, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .ops = &postdiv_reg_ops, + .c = { + .dbg_name = "mmss_mdss_byte1_intf_div_clk", + .parent = &byte1_clk_src.c, + .ops = &clk_ops_slave_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(mmss_mdss_byte1_intf_div_clk.c), + }, +}; + static struct branch_clk mmss_mdss_byte1_intf_clk = { .cbcr_reg = MMSS_MDSS_BYTE1_INTF_CBCR, - .has_sibling = 1, + .has_sibling = 0, .base = &virt_base, .c = { .dbg_name = "mmss_mdss_byte1_intf_clk", - .parent = &byte1_clk_src.c, + .parent = &mmss_mdss_byte1_intf_div_clk.c, .ops = &clk_ops_branch, CLK_INIT(mmss_mdss_byte1_intf_clk.c), }, @@ -2406,8 +2452,10 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = { CLK_LIST(mmss_mdss_ahb_clk), CLK_LIST(mmss_mdss_axi_clk), CLK_LIST(mmss_mdss_byte0_clk), + CLK_LIST(mmss_mdss_byte0_intf_div_clk), CLK_LIST(mmss_mdss_byte0_intf_clk), CLK_LIST(mmss_mdss_byte1_clk), + CLK_LIST(mmss_mdss_byte0_intf_div_clk), CLK_LIST(mmss_mdss_byte1_intf_clk), CLK_LIST(mmss_mdss_dp_aux_clk), CLK_LIST(mmss_mdss_dp_gtc_clk), diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 8fb7e73441bc..bd0ae1388487 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -398,8 +398,10 @@ #define clk_mmss_mdss_axi_clk 0xdf04fc1d #define clk_mmss_mdss_byte0_clk 0x38105d25 #define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 #define clk_mmss_mdss_byte1_clk 0xe0c21354 #define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 #define clk_mmss_mdss_dp_aux_clk 0x23125eb6 #define clk_mmss_mdss_dp_gtc_clk 0xb59c151a #define clk_mmss_mdss_esc0_clk 0x5721ff83 diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h index 22bafd3ee428..9ba814880632 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h @@ -358,8 +358,10 @@ #define MMSS_MDSS_AXI_CBCR 0x02310 #define MMSS_MDSS_BYTE0_CBCR 0x0233C #define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C #define MMSS_MDSS_BYTE1_CBCR 0x02340 #define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 #define MMSS_MDSS_DP_AUX_CBCR 0x02364 #define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C #define MMSS_MDSS_DP_GTC_CBCR 0x02368 |