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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-23 18:30:05 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-26 10:24:50 +0200 |
| commit | b8fc2f6a18052194c486b407765a4f5e4dca692d (patch) | |
| tree | 1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7 /tools | |
| parent | e6f0bfc4fb963da9e945ebc6330db9a4d756ba78 (diff) | |
drm/i915: set the correct eDP aux channel clock divider on DDI
The cdclk frequency is not always the same, so the value here should
be adjusted to match it.
Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions