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| author | xiaonian <xiaonian@codeaurora.org> | 2015-07-16 14:39:32 +0800 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:28:11 -0700 |
| commit | d6a8e003e07e1ebafc596e051defb84194c527a2 (patch) | |
| tree | c8a7fde4fe03bdf66e6521dad8acd4d1e9764dc0 /tools/perf/scripts/python | |
| parent | 34167033d4ab084678f0adc1bf893c80ed290c84 (diff) | |
mmc: core: set REL_WR_SEC_C register to 0x1 per eMMC5.0 spec
Some eMMC vendors violate eMMC 5.0 spec and set REL_WR_SEC_C
register to 0x10 to indicate the ability of RPMB throughput
improvement thus lead to failure when TZ module write data to
RPMB partition. This change will check bit[4] of EXT_CSD[166]
and if it is not set then change value of REL_WR_SEC_C to 0x1
directly ignoring value of EXT_CSD[222].
CRs-Fixed: 866059
Change-Id: Ibd12c94ad691eca1fa3ea2049b750a6e98178678
Signed-off-by: xiaonian <xiaonian@codeaurora.org>
Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions