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| author | Tony Truong <truong@codeaurora.org> | 2016-08-31 14:43:49 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-11-10 18:25:33 -0800 |
| commit | c25e50abe918467fddae119d9b6c2c845bb45a28 (patch) | |
| tree | 80c8389a56e51512a7bf30cc9ad196b8f3dde20a /tools/perf/scripts/python | |
| parent | e95375540c79e0d0b48953141559fec4b6bcbf96 (diff) | |
msm: pcie: support configurable wr halt size for PCIe
Clients of PCIe determine the size and transfer speed of
incoming IP packets. In order to ensure ordering of all
packets, each client requires different PCIe write halt
sizes. Thus, make this PCIe setting configurable.
Change-Id: I208c8c83a8f5ee8efadf01175f60d70fb4bf48cf
Signed-off-by: Tony Truong <truong@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions