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| author | Maya Erez <merez@codeaurora.org> | 2017-03-27 09:31:39 +0300 |
|---|---|---|
| committer | Maya Erez <merez@codeaurora.org> | 2017-03-27 09:31:39 +0300 |
| commit | b30b481b1451cba51220c063a3adb2c64f02a1b7 (patch) | |
| tree | 09dad0e9af1fb90f93ce6813625196d9f9edac0b /tools/perf/scripts/python | |
| parent | ba53c4518c7bf3b3abda54284cfb2a6d2175749b (diff) | |
msm_11ad: 11AD SMMU changes to allow enabling of SMMU stage1
Add the following changes to support enabling of SMMU stage1:
- Enable DMA coherency and PAGE_TABLE_FORCE_COHERENT attr
to allow cache coherency when SMMU stage1 is enabled
- Add the option to define SMMU base address and size in DT
- Add DT node flag to determine if stage1 is enabled
Change-Id: I38b0ee3d5c4bf533f91077ee69bd464dfdd358c8
Signed-off-by: Maya Erez <merez@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions