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| author | Mayank Rana <mrana@codeaurora.org> | 2016-03-29 11:11:28 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-04-04 19:29:28 -0700 |
| commit | b1c51424b14ec2bf4900eb32323166c3e17d110a (patch) | |
| tree | 4c4f11cf9c0bb9fbc42ead863c8e57c64287682d /tools/perf/scripts/python | |
| parent | 1431dc81797891e90c4ea37db4f00665df4fe697 (diff) | |
usb: qmp: phy: Make sure QMP PHY reset write is completed
Add explicit memory barrier after programming USB3_PHY_SW_RESET
register which makes sure that above write is not cached. If
this register write is cached, then phy driver is timing out
with checking PCS status. In some cases, L2 cache memory error
is seen when that register write is flushed whereas usb phy
clock is turned off.
CRs-Fixed: 990963
Change-Id: Iebe8cb4034721e76fa5ea63e33304b9dc0243797
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions