usb: phy: qusb2: Switch to SE clk from diff clk upon suspend

Upon out of XO shutdown due to remote wakeup, as soon as XO gets
restored refclk is supplied to phy before even refgen current
is stabilized. USB3 controller asserts suspend_n signal asynchronously
for remote wake-up scenario solely based on utmi_linestate switching
from J state(suspend) to K state(resume). As a result phy attempts to
lock PLL since all prerequisites are met but, PLL lock attempt fails
and phy gets stuck. Since GCC_RX1_USB2_CLKREF_EN which was supposed to
control differential(CML) clock output to QUSB2 is a no-op, hence switch
to SE clock by PHY CSR controlled mux upon suspend. This prevents refclk
output to go directly to phy upon XO restore and prevents premature phy
pll locking. Phy PLL actually gets locked when phy driver switches back
from SE clk to diff clk.

Change-Id: Ie5474c42ccdd88df4c101b2113ca8d924eddf037
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>

0 files changed, 0 insertions, 0 deletions