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| author | Karthikeyan Mani <kmani@codeaurora.org> | 2017-04-04 10:32:01 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-04-04 10:40:42 -0700 |
| commit | 7882bb6e55aad3414581c1a7c0c9565653f4014c (patch) | |
| tree | 55cdcbe73c6124711479053ffe041be490aab1a2 /tools/perf/scripts/python | |
| parent | 4c332132fc72dd634004f76d92534995feaad15c (diff) | |
ASoC: msm: Update proper clock frequency for slave mode
Clock framework in LPASS expects valid clock frequency
for slave mode (EBIT) as well. This is required to maintain
corresponding voltage as per respective frequencies by clock
team in frequency plan. Avoid sending zero clock frequency
in clock enable even though it is slave mode.
Change-Id: If3d6ac4f1e7ce2032dbaa0e0475e8e1abd2692e8
Signed-off-by: Karthikeyan Mani <kmani@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions