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authorAjay Agarwal <ajaya@codeaurora.org>2017-11-01 11:20:03 +0530
committerGerrit - the friendly Code Review server <code-review@localhost>2018-09-29 10:58:06 -0700
commit6dbc7675bc6332e9fde918faa2a1b70d625234e3 (patch)
tree0fe28a55a58627f1a8f60a7f8051496d8de26e63 /tools/perf/scripts/python
parentd1203d1a8b126677826f165ced9755878f7529d5 (diff)
USB: dwc3: gadget: Fix TxFIFO resizing logic
The TxFIFO RAM start address for some USB controller might be non-zero. The current FIFO resizing logic in place always considers that this start address is 0x0000 and writes the RAM start address for subsequent TxFIFOs with the last FIFO depth only, leading to the controller not functioning properly. To make the controller work, start address of GTXFIFOSIZ(#n) should be written with the start address of GTXFIFOSIZ(0) + last FIFO depth. Fix the resizing logic accordingly. Change-Id: Ia83edef7165b980828f2a43832493be2349ae0dc Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
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