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| author | Sandeep Panda <spanda@codeaurora.org> | 2016-11-18 14:20:06 +0530 |
|---|---|---|
| committer | Sandeep Panda <spanda@codeaurora.org> | 2016-12-16 15:51:27 +0530 |
| commit | 6a21dcc9bf61ffbb511b7d58b2744ee1b8cfddef (patch) | |
| tree | 85cf99f72adb9f0f9586d84b514e28864a4da188 /tools/perf/scripts/python | |
| parent | 3162449f7d245d45f007d4ea3224576ddf1bcc63 (diff) | |
clk: qcom: add common clock framework support for MDSS PLL
Model and configure MDSS DSI PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clcoks
as per common clock infrastructure.
Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions