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| author | Laxminath Kasam <lkasam@codeaurora.org> | 2017-04-03 16:40:56 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-04-06 23:58:25 -0700 |
| commit | 44a8756de994892321073e35e65cffa927c996fe (patch) | |
| tree | d449acc36b545b7f6225da8222e9a9bff7c5c79f /tools/perf/scripts/python | |
| parent | 6319cf033ba2da8fdbdfcbdd159b20450a871726 (diff) | |
ASoC: msm: Update proper clock frequency for slave mode
Clock framework in LPASS expects valid clock frequency
for slave mode (EBIT) as well. This is required to maintain
corresponding voltage as per respective frequencies by clock
team in frequency plan. Avoid sending zero clock frequency
in clock enable even though it is slave mode.
CRs-Fixed: 2028063
Change-Id: Ie9c28a921ee7bbeda67b0591f0caf0a88ea2d19c
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions