diff options
| author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | 2012-09-27 19:13:06 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-09-28 17:02:08 +0200 |
| commit | 2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8 (patch) | |
| tree | 6a0050828820fb80994bfbcba81ae388534257ca /tools/perf/scripts/python | |
| parent | 74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10 (diff) | |
drm/i915: Enable DisplayPort in Valleyview
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: drop spurious whitespace changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions