clk: qcom: mdss: update the clk_ops for dp_vco_divided_clk_src_mux

The fractional divider values for DP pixel clock RCG needs to be
determined dynamically. Add the recalc_rate operation for the DP
PLL mux clock dp_vco_divided_clk_src_mux which is the parent of
DP pixel clock RCG. This enables the RCG clock to calculate the
fractional dividers correctly. Modify the determine rate op for the
mux clock to also set the new parent after performing the determine
rate operation.

Change-Id: Id931a60677380ecee28eb9aec6468548898b812b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

0 files changed, 0 insertions, 0 deletions