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| author | Sahitya Tummala <stummala@codeaurora.org> | 2013-12-17 11:47:32 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 10:56:25 -0700 |
| commit | e02263415973fdf0b8c31c125280cb59c93647a0 (patch) | |
| tree | a44060c5e49b0adf6741f83e680bee05a9a8f4db /tools/perf/scripts/python/syscall-counts.py | |
| parent | 7686ac5a4abde2b5abae661299805b39cc578615 (diff) | |
scsi: ufs-msm: Enable clock gating
Enable relevant PHY clocks to be turned off as part of ufshcd
clock gating. Also, enable clock gating by setting necessary
capabilities.
The clock gating delay is currently set to 150ms by default. It can
be changed if required via sysfs -
echo xx > /sys/bus/platform/devices/msm_ufs.1/clkgate_delay_ms
Change-Id: I41c0b4c560711540cc0630e752d7843fca3fb26c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions