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| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-11-01 10:46:59 -0700 |
|---|---|---|
| committer | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-11-01 13:53:35 -0700 |
| commit | 5fa9ed4664b35e7563b9f0e2f8a2a453ffa15462 (patch) | |
| tree | 77c78f7fd6bcc046a7fb2661dcac9d947139ea59 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 9a5e4de1022b15364b14eee9bb09cfcda1601eb7 (diff) | |
clk: msm: clock-debug: Print VDD level in clock_state traces
Add support for printing the voltage voting info to the
clock_state ftrace events.
CRs-Fixed: 1082843
Change-Id: I6ab3992958a659995b7d5020287fd6e47e28f2a4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions