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| author | Meng Wang <mwang@codeaurora.org> | 2016-09-07 11:02:38 +0800 |
|---|---|---|
| committer | Meng Wang <mwang@codeaurora.org> | 2016-09-15 18:22:11 -0700 |
| commit | 26b1f0d3370b95575fc1fcdbf670f05c17a55cba (patch) | |
| tree | 6ae0da8e726641c9aa2999733759300784cc5368 /tools/perf/scripts/python/sched-migration.py | |
| parent | d2afad6a903bdda2f803fae49f0b0001d12f8600 (diff) | |
ASoc: wcd934x: correct High-Z mode for dmic pins
Update the DMIC CLK and DATA registers to use the correct
settings required for DMIC High-Z on wcd934x. Registers
should be set to 0x6 for Slimbus mode and 0xD for I2C mode.
CRs-Fixed: 1059712
Change-Id: Ibe8ca2e40ee56708e8c84c174d12ce5841e6b1ce
Signed-off-by: Meng Wang <mwang@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions