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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-08-08 21:51:10 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-08-08 20:53:37 +0200
commitf45651bae2ee73ae551699d481f76aa6ad92138f (patch)
treef649e40089135c23572ddcf6c7a622ccd99e24ce /tools/perf/scripts/python/netdev-times.py
parent4fa790421c10e5c9c62406655c06d97a94555d54 (diff)
drm/i915: Eliminate rmw from .update_primary_plane()
Move the entire DSPCNTR register setup into the .update_primary_plane() functions. That's where it belongs anyway and it'll also help 830M which has the extra problem that plane registers reads will return the value latched at the last vblank, not the value that was last written. Also move DSPPOS and DSPSIZE setup there. v2: Don't move variable initialization to avoid churn later Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
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