diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-01 18:10:53 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-02 13:24:37 +0200 |
| commit | b0e77b9c6b2fc21ec2e3d8b54edf8757a7c6a8dd (patch) | |
| tree | b683f553f6deaaee484cdfd9782a001fe9263351 /tools/perf/scripts/python/netdev-times.py | |
| parent | 749052fba650a644b29ed2ae35cd985f736401b3 (diff) | |
drm/i915: extract intel_set_pipe_timings from crtc_mode_set
Version 2: call intel_set_pipe_timings from both i9xx_crtc_mode_set
and ironlake_crtc_mode_set, instead of just ironlake, as requested by
Daniel Vetter.
The problem caused by calling this function from i9xx_crtc_mode_set
too is that now on i9xx we write to PIPESRC before writing to DSPSIZE
and DSPPOS. I could not find any evidence in our documentation that
this won't work, and the docs actually say the pipe registers should
be set before the plane registers.
Version 3: don't remove pipeconf bits on i9xx_crtc_mode_set.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions
