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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-12-01 20:27:21 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-01-09 08:07:43 +0100 |
| commit | 9d9541d44a26dea009247e001ebd7775e2feeb37 (patch) | |
| tree | a1352952598d9f6de671337095076d4ca91596f9 /tools/perf/scripts/python/netdev-times.py | |
| parent | e01b04be3eb00456d65278cfa56cfd8103872bfb (diff) | |
clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
commit 68af4fa8f39b542a6cde7ac19518d88e9b3099dc upstream.
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.
Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions