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| author | Archana Sathyakumar <asathyak@codeaurora.org> | 2016-03-25 15:36:47 -0600 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-04-05 11:28:56 -0700 |
| commit | 668a7726758e7cc43b28fe1b723f55db652271fb (patch) | |
| tree | 7d0fbf59166490336583ccbd53083dd64a5e4aaa /tools/perf/scripts/python/netdev-times.py | |
| parent | dde29b75ebd015551120bed2be1bf5eb66081a06 (diff) | |
ARM: dts: msm: Support AVS_CTL register write for msmcobalt
CPRh communicates voltages to the PMIC via L2 SAW4.
APCLUS{0,1}_L2_SAW4_AVS_CTL/LIMIT registers need to be programmed for
CPRh operation.
CRs-fixed: 987593
Change-Id: I635d710759a94e2bb29fd3c7811816d09243de50
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions