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authorAlex Deucher <alexander.deucher@amd.com>2012-10-22 13:04:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-25 17:50:33 -0400
commit605de6b97e82934f37480446099d6a7453f2e964 (patch)
tree1df600c6621f5b562a8e44b9c57b067822f2c2c1 /tools/perf/scripts/python/netdev-times.py
parent21a93e130d4b3b8c6a45fa27d2678e91ad2ace7d (diff)
drm/radeon: implement async vm_flush for the sDMA (v6)
Update the page table base address and flush the VM TLB using the sDMA. V2: update for 2 level PTs V3: update vm flush V4: update SH_MEM* regs V5: switch back to old style VM TLB invalidate V6: fix packet formatting Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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