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| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-06-16 11:10:19 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-08-10 11:49:28 +0200 |
| commit | 1cee72ed4856504fd597145ce10b29751c4d27a1 (patch) | |
| tree | 3e8a6aeb1b65e4131540d930a5666e9d1201d5cf /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 63b9e0f32f72892de7064c6888484b881ddbb42f (diff) | |
can: c_can: Update D_CAN TX and RX functions to 32 bit - fix Altera Cyclone access
commit 427460c83cdf55069eee49799a0caef7dde8df69 upstream.
When testing CAN write floods on Altera's CycloneV, the first 2 bytes
are sometimes 0x00, 0x00 or corrupted instead of the values sent. Also
observed bytes 4 & 5 were corrupted in some cases.
The D_CAN Data registers are 32 bits and changing from 16 bit writes to
32 bit writes fixes the problem.
Testing performed on Altera CycloneV (D_CAN). Requesting tests on other
C_CAN & D_CAN platforms.
Reported-by: Richard Andrysek <richard.andrysek@gomtec.de>
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions