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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-04-30 16:39:20 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-08 13:03:35 +0200 |
| commit | 6222709d60734dd1e11f8d24520d9f23b4eb953e (patch) | |
| tree | dea715d2e0caeb6960df4622064f3e9926a21ef5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 57520bc55cf56b77e7a67cb0877fafdb65181f6a (diff) | |
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
the PLLS power domain to ensure those two power wells are up.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions