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| author | Vijayavardhan Vennapusa <vvreddy@codeaurora.org> | 2017-07-28 11:23:47 +0530 |
|---|---|---|
| committer | Vijayavardhan Vennapusa <vvreddy@codeaurora.org> | 2017-08-04 17:05:55 +0530 |
| commit | e9ee6bea1eb88e73bed98adadda314998103b424 (patch) | |
| tree | 58d0d89b778aa19bd925771e232bac61c873fa6f /tools/perf/scripts/python/cs-trace-disasm.py | |
| parent | e29d253ecf0480d4359ce41503741783d803ed6b (diff) | |
dwc3-msm: Add delay between consecutive register reads in while loop
Add some delay between two consecutive register reads in while loop
so that to avoid traffic congestion on NOCs.
Change-Id: I6efb8c91e0d07160ccce593a23898b2259cb1ebf
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions