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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-27 15:50:28 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 23:50:57 +0100 |
| commit | fff367c752f5fb998882c7bc0a213ab1e53857db (patch) | |
| tree | 8e1be4691dfd4e0659bdb9f1dd020894cd5b8239 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | cd986abbac6044c76b95fd512bc62329ef9959d0 (diff) | |
drm/i915: clarify why we need to enable fdi plls so early
For reference, see "Graphics BSpec: vol4g North Display Engine
Registers [IVB], Display Mode Set Sequence", step 4 of the enabling
sequence:
a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
b. "Switch from Rawclk to PCDclk in FDI Receiver
c. "Enable CPU FDI Transmitter PLL, wait for warmup"
Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions