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| author | Guchun Chen <guchunc@codeaurora.org> | 2018-02-28 13:47:49 +0800 |
|---|---|---|
| committer | Guchun Chen <guchunc@codeaurora.org> | 2018-03-07 11:10:56 +0800 |
| commit | cf8812ee6ea8ff192d9d0e50957caa25638525f6 (patch) | |
| tree | 61b05564a11daeeee748e48066a8ccb3388e27d4 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 1707cb3ff140dec01127669e1c88d5b850f272e4 (diff) | |
clk: qcom: mdss: improve DSI PLL's performance
To improve performance margin for DSI's PLL at cold temperature case,
the value of DSIPHY_PLL_PLL_ICPMSET should be changed from 0x24 to 0x3f.
Change-Id: I139e37e137355c5e8f0b3bebd28b23a09593dd13
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions