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| author | Imre Deak <imre.deak@intel.com> | 2015-03-26 17:35:40 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-04-09 15:57:46 +0200 |
| commit | 46ec15f2662b48103751ea059d2cb4e2571bad5e (patch) | |
| tree | 1c3309b425f0c5f29129bee08ae624429a13599a /tools/perf/scripts/python/check-perf-trace.py | |
| parent | ce89db2eabb0979e823aed38d5f5b22512d06392 (diff) | |
drm/i915: use proper FBC base register on all new platforms
Starting from GEN5 the FBC base register is the same on all platforms.
GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
things work on BXT as well.
Motivated by Rodrigo's request to check FBC support on BXT.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions