diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-05-11 11:46:49 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-05-27 14:52:13 -0700 |
| commit | b96f15ac0788ef2ef4b2bdea7e088195fabda54c (patch) | |
| tree | 8496c63852009660b98a9e93a990bec100dc64d6 /tools/perf/scripts/python/bin | |
| parent | d98ad5e9f4ca59bdface89b50c81a2aaacb510e6 (diff) | |
clk: msm: mdss: fix DP register configurations
This change provides the below updates:
- Current DP PLL driver uses the pll_base and the base
address for the TXn registers instead of phy_base address.
Fix this by using the correct base address.
- Disable handoff for vco_divided_clk
by implementing handoff function for this clock.
- Update the PLL settings to fix PLL locking issues.
CRs-Fixed: 1009740
Change-Id: Iea46c5b0482bceb841309175ede42ec3be3e20fd
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions