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| author | Vijay Viswanath <vviswana@codeaurora.org> | 2016-11-02 16:17:30 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-01-17 01:37:34 -0800 |
| commit | 6d15d790dcc42b666cd33f99711f9bae55be9142 (patch) | |
| tree | 46c2d966e6214f660ab73cabcaf60e20adba8bdb /tools/perf/scripts/python/bin | |
| parent | 4b3736890b25b8af6a8468f13ef8a310c7468a92 (diff) | |
MMC : host: clear interrupt after halt in case of error
During error scenario, if interrupt status of CQ controller is cleared
before halting the controller, the CQ controller can send commands to
card in the time delay between clearing of interrupt and halting. The
response of card to these commands can overwrite the error information
stored in Response Arg register. So, if an error is detected, the CQ
must be halted first and then the interrupt must be cleared.
Change-Id: Ief7039226b01b50fc71cf17a4eb625afd8c9bd06
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions