clk: msm: mdss: change DP clock rate in order of KHz

Certain frequencies of DP VCO clock are more than 4.29 GHz
and are not supported by clock framework on 32 bit builds,
since it exceeds the maximum value of unsigned long data type.
To fix this issue, change the DP link clock frequencies in order
of KHz in DP FB driver/MMSS cobalt clock driver/DP PLL driver.

Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

0 files changed, 0 insertions, 0 deletions