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authorPadmanabhan Komanduru <pkomandu@codeaurora.org>2017-06-23 16:44:31 +0530
committerPadmanabhan Komanduru <pkomandu@codeaurora.org>2017-10-10 18:20:13 +0530
commit54d865e4839fad4f725d35cf0646f0c44e65864d (patch)
tree3aac42a306d4f28c36f98b602afd23ecf9d9d157 /scripts/basic/bin2c.c
parenta7bf109995f056098492cadcf917eaa939f8286c (diff)
mdss: dp: set the proper parent for dp_vco_divided_clk_mux
The DP VCO divided mux clock has two parent dividers div_two and div_four. The parent for this needs to be set based on the link rate frequency as per the hardware programming guide and not based on the auto PLL calculation logic. Add support to set the correct parent for this. Change-Id: Ia2d340a4e8790d90161c1f4a7c8273449fa3f53c Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Diffstat (limited to 'scripts/basic/bin2c.c')
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