msm: mdss: re-configure DP mainlink clocks during link training

During clock recovery sequence of DP link training, at the end of
first iteration, if the maximum voltage swing or retry count of 5
is reached, the link rate needs to be reduced and the link training
sequence need to be tried again. The current implementation sends
the AUX command to specify the reduced bandwidth but doesn't actually
reduce the link rate. This causes link training failures during
compliance testing. Add change to disable the DP mainlink clocks and
re-enable them with reduced rate in such cases.

Change-Id: I873799a89871dd144434e5692f38434795e686f1
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>

0 files changed, 0 insertions, 0 deletions